A low voltage drive circuit includes a transmit analog to digital circuit that converts transmit digital data into analog outbound data by: generating a DC component; and generating an oscillating component at a first frequency that conveys the transmit digital data, wherein the magnitudes of both the oscillating component and the DC component are limited to a range that is less than a difference between the magnitudes of the power supply rails of the circuit, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at a first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

In one embodiment, a current source is coupled to a channel input of a switch, and an output of the switch is coupled to a positive or negative data line in a USB 2.0 communication system. In addition, a first input of the voltage threshold comparator is coupled to the negative data line, a second input of the voltage threshold comparator is coupled to a positive data line, and an output of the voltage threshold comparator is coupled to a control input of the switch.

Data transmission method for a two-wire data bus from a transmitter having ports to a receiver having ports. The method comprises the steps of: detecting a first common-mode voltage swing on the ports and forming a first common-mode signal. Detecting a second common-mode voltage swing on the ports and forming a second common-mode signal. The transmitter sending data via the two-wire data bus. The receiver receiving the data. The voltage difference on the ports being compared with a lower and an upper reception threshold, wherein an output of an apparatus element assumes a first or second level on the basis of this comparison. Raising the differential send level if the absolute value of the first common-mode signal is greater than a first threshold value. Raising the upper reception threshold and/or lowering the lower reception threshold if the absolute value of the second common-mode signal is greater than a second threshold value. The method allows the transmission of a datum from the transmitter to the receiver. On the basis of the result of the comparison of the absolute value of the detected first common-mode signal with a first threshold value, the upper reception threshold is raised and/or the lower reception threshold is lowered whenever this absolute value of the first common-mode signal is greater than this first threshold value.

A low voltage drive circuit includes a transmit analog to digital circuit that converts transmit digital data into analog outbound data. A receive analog to digital circuit converts analog inbound data into received digital data. A drive sense circuit is configured to: convert the analog outbound data into an analog transmit signal; drive the analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at a first frequency; receive an analog receive signal from the bus; and isolate the analog receive signal from the analog transmit signal to recover the analog inbound data, wherein the analog inbound data is represented within the analog receive signal as variances in loading of the bus at a second frequency.

A transmitter for providing channel equalization that includes a first driver and second driver having a high pass filter. The first driver generates a first output signal representing a digital input signal. The second driver generates a second output signal representing a high pass filtered version of the digital input signal. The first and second output signals are summed to provide a third output signal that is channel equalized for transmission over a channel.

A transmitter for establishing communication between a device and a differential network bus includes current driving means connected to each of the two conduction lines of the differential network bus, through a first and second conduction paths of the transmitter; at least one unidirectional current regulator for extracting a first current equal to a known ratio of a parasitic current circulating through the first conduction path, with a direction inverse to the driving current through the conduction path connected to one of the lines of the differential bus; means for obtaining, from the first current, a second current with a magnitude equal to the original magnitude of the parasitic current; and means for introducing the second current into the second conduction path connected to the other line of the differential bus.

In an optocoupler circuit, a first direction path, which transmits signals from a first to a second terminal, includes a first level shifter, a second level shifter, and a first optocoupler. The first level shifter receives a first input signal at the first terminal, and shifts a voltage level of the first input signal to a first shifted voltage level with respect to a first ground level in a first power domain, to provide a first shifted signal. The first optocoupler receives the first shifted signal, and generates a first optocoupler signal in response to the first shifted signal. The second level shifter receives the first optocoupler signal, and shifts a voltage level of the first optocoupler signal to a second shifted voltage level with respect to a second ground level in a second power domain, to provide a second shifted signal at the second terminal.

A PoDL system conducts differential data and DC power over the same wire pair, and various DC coupling techniques are described that improve DC voltage coupling while attenuating AC common mode noise. Pairs of differential mode chokes (DMCs) are used to share current supplied by a power supply. In one embodiment, one DMC is coupled to the line side of a common mode choke (CMC), and one DMC is coupled to the PHY side of the CMC. The line-side DMC has windings that are loosely magnetically coupled so that DMC does not present a very low impedance to AC common mode noise on the wires. Therefore, the performance of the wires' RC termination circuitry is not adversely affected by the line-side DMC when minimizing reflections of common mode signals. The DMCs may use the same magnetic core, and the CMC may be series CMCs that used the same magnetic core.

Data transmission method (d) for a two-wire data bus (Z) from a transmitter (S) having ports (A1, A2) to a receiver (E) having ports (A3, A4). The method comprises the steps of: detecting a first common-mode voltage swing on the ports (A1, A2) and forming a first common-mode signal (k1). Detecting a second common-mode voltage swing on the ports (A3, A4) and forming a second common-mode signal (k2). The transmitter (S) sending data via the two-wire data bus (Z). The receiver (E) receiving the data. The voltage difference on the ports (A3, A4) being compared with a lower and an upper reception threshold (SW4, SW5), wherein an output (0) of an apparatus element (CMP2) assumes a first or second level on the basis of this comparison. Raising the differential send level if the absolute value of the first common-mode signal (k1) is greater than a first threshold value (SW1). Raising the upper reception threshold (SW5) and/or lowering the lower reception threshold (SW4) if the absolute value of the second common-mode signal (k2) is greater than a second threshold value (SW2). The method allows the transmission of a datum from the transmitter (S) to the receiver (E). On the basis of the result of the comparison of the absolute value of the detected first common-mode signal (k1) with a first threshold value (SW1), the upper reception threshold (SW5) is raised and/or the lower reception threshold (SW4) is lowered whenever this absolute value of the first common-mode signal (k1) is greater than this first threshold value (SW1).

Methods, systems, and devices for operating memory cell(s) using adapting the current on a channel are described. A current on a channel may be adapted during a transition period between signaling a first logic value over the channel and signaling a second (e.g. subsequent) logic value over the channel. Adapting the current may include increasing or decreasing the current on the channel during the transition period. The degree of adaptation may be based on a difference between the first logic value and the subsequent logic value. In some cases, a logic circuit may be configured to determine a difference between the first and subsequent logic value. The logic circuit may be further configured to communicate the difference to an adaptive driver. And the adaptive driver may adapt a current of the channel based on the communicated difference.