An integrated circuit includes a differential signal driver that receives a first signal from a first input terminal, receives a second signal, which is a differential signal of the first signal, from a second input terminal, outputs a first output signal corresponding to the first signal to a first output terminal, and outputs a second output signal corresponding to the second signal to a second output terminal. The integrated circuit further includes a first capacitor unit connected to the first output terminal and controlling a slew rate of the first output signal based on a first capacitance, a second capacitor unit connected to the second output terminal and controlling a slew rate of the second output signal based on a second capacitance, and a phase selection unit that receives the first signal and provides the first signal to the second capacitor unit, and that receives the second signal and provides the second signal to the first capacitor unit, so as to control the slew rates of the first and second output signals.

A driver circuit includes a first inverter, a bias-control circuit, and a second inverter. The first inverter, which is connected between a first supply voltage and ground, receives an input data signal and generates an inverted version of the input data signal. The bias-control circuit, which is connected between a second supply voltage and the first inverter, receives the inverted version of the input data signal and a bias signal, and generates a level-shifted data signal based on the inverted version of the input data signal, the bias signal, and the second supply voltage. The bias-control circuit reduces a difference between voltage levels of the second supply voltage and the inverted version of the input data signal. The second inverter is connected between the second supply voltage and ground, and further connected to the bias-control circuit and first inverter and generates an output data signal.

A CAN module comprising a bit duration compensation component arranged to generate a compensated transmit command signal for controlling the driver component to drive a dominant state on the CAN bus. The compensated transmit command signal comprises dominant bits of a compensated-bit duration T.sub.bit.sub._cp=T.sub.bit.sub._Tx+tc, wherein tc comprises a compensation offset derived at least partly from a difference between a transmit-bit duration of a digital transmit command signal and a receive-bit duration of a received data signal.

Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period proceeding the first portion.

A circuit (200, 300, 400, 600, 700, 800) interfacing a device (20, 30, 40, 60, 80) with a line-pair includes: a diode bridge (210) having polarity-independent input terminals coupled to the line-pair; a galvanic isolation device (230, 330) receiving a transmit signal and coupling the transmit signal to its output; a variable edge delay circuit (270, 370, 572, 574, 576) that delays rising/falling edges of the transmit signal more than falling/rising edges of the transmit signal; a voltage-controlled variable resistance element (260, 360, 460) connected across output terminals of the diode bridge; and a filter connected to a control terminal of the voltage-controlled variable resistance element. The filter includes decoupled charge and discharge paths to decouple the rise time of the transmit signal from the fall time of the transmit signal. The voltage-controlled variable resistance element couples the transmit signal to the line-pair via the diode bridge.

A pre-driver circuit is provided. The pre-driver circuit includes a switch circuit, a common-mode voltage control circuit, and a current supply circuit. The switch circuit receives differential input signals, outputs differential output signals, and controls switching between a high level and a low level of the differential output signals and the differential input signals. The common-mode voltage control circuit is coupled to the switch circuit. The common-mode voltage control circuit receives a reference voltage and controls a common-mode voltage of the differential output signals according to the reference voltage. The current supply circuit is coupled to the switch circuit and the common-mode voltage control circuit. The current supply circuit provides a driving current for the switch circuit and the common-mode voltage control circuit.

A high-speed serial interface includes a transmitter having an output module with settings that select an output impedances of the output module and a tuning value for the output impedance, and a receiver having a plurality of compensation modules each to provide a selectable level of equalization to a data bitstream from the transmitter, and a control module that directs the transmitter to successively select each of the tuning values, that directs the compensation modules, for each tuning value, to successively select each of the levels of equalization, that evaluates an indication of a performance level of the receiver for each of the successively selected levels of equalization and for each of the tuning values, and that selects a particular tuning value based upon the indications of the performance level of the receiver.

Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of calibration includes configuring a 3-phase signal to include a high frequency component and a low frequency component during a calibration period, and transmitting a version of the 3-phase signal on each wire of a 3-wire interface. The version of the 3-phase signal transmitted on each wire is out-of-phase with the versions of the 3-phase signal transmitted on each of the other wires of the 3-wire interface. The 3-phase signal may be configured to enable a receiver to determine certain operating parameters of the 3-wire interface.

An apparatus includes an interface and a circuit. The interface may be configured to generate a read signal that carries read data from a memory channel. The circuit may be configured to (i) modify the read signal with a de-emphasis on each pull up of the read signal and a pre-emphasis on each pull down of the read signal and (ii) transfer the read signal as modified to a memory controller.

The present disclosure discloses a method of transmitting a signal, a wearable communication device and a terminal device. The method includes: receiving, by a wearable communication device, a modulated wave signal transmitted by a terminal device; demodulating the modulated wave signal to obtain a to-be-decoded signal; performing a waveform shaping process on the to-be-decoded signal to obtain a square wave signal, where a high level in the square wave signal is configured to represent a first preset value, and a time interval is existed between two high levels corresponding to any two adjacent first preset values; acquiring time interval eigenvalues in the square wave signal; acquiring a one-to-one mapping relation of the interval eigenvalues and a plurality of coding sequences; and performing, according to the time interval eigenvalues and the mapping relation, a first decoding process and a second decoding process on the square wave signal to obtain original data.