H04L25/029

BUS FAILURE DETECTION TRANSCEIVER ARCHITECTURE AND TRANSCEIVER OPERATION METHOD
20180189129 · 2018-07-05 ·

This application relates to a method of operating a transceiver for imparting a voltage signal on a differential signaling bus, wherein the transceiver comprises an output terminal and a string of one or more transistors connected between the output terminal and a predetermined voltage level, and wherein the transceiver can be switched between an active state in which the predetermined voltage level is applied to the output terminal, and an inactive state in which the predetermined voltage level is not applied to the output terminal. The method comprises a detection step of detecting a first quantity depending on a current flowing through a first transistor in the string of transistors, a failure determination step of determining whether the detected first quantity satisfies one or more error conditions, and a control step of switching the transceiver to the inactive state if the detected first quantity is determined to satisfy at least one of the one or more error conditions. The application further relates to a transceiver for imparting a voltage signal on a differential signaling bus.

SYSTEM ARCHITECTURE AND METHOD FOR DYNAMICALLY OPTIMIZED IMPEDANCE MATCHING FOR ANTENNA FEEDS
20240405431 · 2024-12-05 ·

A communication system applies impedance matching to an antenna specific to individual samples of a transmit signal. The system samples a signal and identifies the peak frequency content of each sample. Based on the peak frequency content, the system identifies an impedance match for a given antenna that provides the greatest energy transmission. The sampled portion of the signal is delayed to accommodate processing time to determine the impedance match and control settings. Control settings may be applied via discrete digital circuitry or continuous analog circuitry.

Circuits and Methods Providing High-Speed Data Link with Equalizer

Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but- for the equalizer.

Circuits and methods providing high-speed data link with equalizer

Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but for the equalizer.

Driving Data of Multiple Protocols Through a Single Set Of Pins

Embodiments of the invention are generally directed driving data of multiple protocols through a single set of pins. An embodiment of an apparatus includes a transmitter connected to two pads on an IC the transmitter including a differential driver to transmit a differential signal, wherein the differential driver has a first branch and a second branch, each branch of the differential driver including a protection device connected to one of the pads; and a common mode driver to transmit a common mode signal, the common mode driver having a first branch and a second branch, each of the branches of the common mode driver including a protection device connected to one of the pads. The first and second switch devices are not turned on simultaneously, based on data to be transmitted, one of the switch devices being turned on and the other being turned off. The third and fourth switch devices are both turned on when the common mode signal is one of a logic HIGH or logic LOW and both turned off when the common mode signal is the other of a logic HIGH or logic LOW.

System architecture and method for dynamically optimized impedance matching for antenna feeds

A communication system applies impedance matching to an antenna specific to individual samples of a transmit signal. The system samples a signal and identifies the peak frequency content of each sample. Based on the peak frequency content, the system identifies an impedance match for a given antenna that provides the greatest energy transmission. The sampled portion of the signal is delayed to accommodate processing time to determine the impedance match and control settings. Control settings may be applied via discrete digital circuitry or continuous analog circuitry.