A low voltage differential signaling receiver includes a resistor load pair, an input stage, a current mode logic stage and a comparator circuit. The input stage includes a P-type transistor pair and a N-type transistor pair. The P-type transistor pair and the N-type transistor pair are configured to generate first differential output voltages on the resistor load pair according to differential input signals. The current mode logic stage is configured to enhance a gain of the first differential output voltages into second differential output voltages. The latch circuit is configured to generate third differential output voltages according to the second differential output voltages and latch the third differential output voltages. The comparator circuit is configured to compare the third differential output voltages and generate a single-ended output signal.

A calibration circuit includes a replica summing circuit, a replica sampling circuit and a control circuit. The replica summing circuit is a replica of a sampling circuit in a serializer/deserializer (SerDes) interface and is configured to provide a summer output signal that is representative of a common mode voltage at an input of the SerDes interface. The replica sampling circuit is a replica of a sampling circuit in the SerDes interface. The replica sampling circuit includes a first input transistor having a gate coupled to the summer output signal and a second input transistor configured to provide an internal reference voltage at its drain. The drain of the second input transistor is coupled to a gate of the second input transistor. The control circuit is configured to control current flow in the replica summing circuit in response to a calibration signal output by the replica sampling circuit.