The present disclosure provides a gate driver on array (GOA) circuit, including a plurality of cascaded GOA circuit units. The GOA circuit of the present disclosure changes drains of T7 and T9 to DC VDD and adds T11 and T12 between Q1 and T7 and T9, which can eliminate an effect to Q1. When CLK1 and CLK2 are high, T11 and T12 are turned on, and Vg (n) and Vg (n+1) output high electrical potential. In the meantime, bootstrap capacitors C3 and C4 are added. When CLK is high, gates of T7 and T9 are pulled up to ensure lossless output of VDD. Therefore, an influence to Q1 when pulling down one row is eliminated. In the meantime, addition of bootstrap capacitors further ensures lossless output of T7 and T9.

System and methods for shaped single carrier orthogonal frequency division multiplexing with low peak to average power ratio are provided. The system receives an input signal and modulates the input signal to form Dirichlet kernels in a time domain to generate an offset Dirichlet kernel output time array where each Dirichlet kernel has a main lobe and a plurality of side lobes. Modulating the input signal suppresses a peak to average power ratio of the offset Dirichlet kernel output time array by reducing the plurality of side lobes of each Dirichlet kernel and respective amplitudes of the side lobes.

The present disclosure provides a gate driver on array (GOA) circuit, including a plurality of cascaded GOA circuit units. The GOA circuit of the present disclosure changes drains of T7 and T9 to DC VDD and adds T11 and T12 between Q1 and T7 and T9, which can eliminate an effect to Q1. When CLK1 and CLK2 are high, T11 and T12 are turned on, and Vg (n) and Vg (n+1) output high electrical potential. In the meantime, bootstrap capacitors C3 and C4 are added. When CLK is high, gates of T7 and T9 are pulled up to ensure lossless output of VDD. Therefore, an influence to Q1 when pulling down one row is eliminated. In the meantime, addition of bootstrap capacitors further ensures lossless output of T7 and T9.

The disclosed systems, structures, and methods are directed to a single-stage frequency-domain equalization (FDEQ) structure implemented on a processor, comprising a data preprocessing unit configured to concatenate received data samples in time-domain digital signals, transform the concatenated data samples in the time-domain digital signals to frequency-domain digital signals, and an adaptive equalizer comprising 2×2 multiple-input multiple output (MIMO) configured to compensate for non-time-varying fixed impairments and time-varying adaptive impairments in the frequency-domain digital signals.

An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.

Apparatuses, systems, and techniques to perform signal processing operations in a fifth generation (“5G”) radio signal. In at least one embodiment, one or more processors equalize, in parallel, one or more 5G radio signals.

An OFDM communication system, includes: a smoothing filter; an equalizer; processors; and a memory containing instructions causing the processors to perform steps of: providing to the smoothing filter a plurality of channel response estimates, each corresponding to a symbol and a channel; receiving a plurality of filtered channel response estimates, each corresponding to a value of the channel response estimate; calculating a plurality of error vectors, each having a plurality of error values, each error value being a difference between the channel response estimate and the filtered channel response estimate; obtaining a mean error vector having a plurality of mean error values, each corresponding to a subcarrier for all symbols; calculating a power of each subcarrier based on the mean error values of the mean error vector; comparing the power of each subcarrier to a threshold power; and adjusting the bandwidth of the smoothing filter based on the comparison.

A pseudo low intermediate frequency (IF) configuration is provided for a receiver having a zero IF radio architecture dedicated for radar detection, in order to reduce false radar detection. Energy from local oscillator leakage is shifted away from DC. After filtering out of the desired sub-channel, the local oscillator leakage energy is suppressed, reducing false radar detection.

This disclosure describes systems, methods, and devices related to extreme high throughput (EHT) data scrambler. A device may determine an extreme high throughput (EHT) data field of a frame to be scrambled using an EHT data scrambler. The device may determine to initialize the EHT data scrambler using an initialization seed, wherein the initialization seed has a size greater than seven bits. The device may generate scrambled data using the initialization seed. The device may cause to send the frame comprising the scrambled data to a first station device.

A channel estimation method of a steel penetration system is configured to reduce computational complexity and required memory. The method includes: reconstructing, at a receiving end, a channel estimation with a compressed-sensing sparse reconstruction algorithm according to a received pilot signal to obtain estimation values of a channel state response of the steel penetration system; and equalizing a received signal of the receiving end according to the estimation values of the channel state response to obtain an equalized signal.