In an example, the present invention includes an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. In an example, the device has a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

Each transmitting apparatus transmits the same radio signals a plurality of times. A communication apparatus includes a plurality of antennas, a signal storage unit, a reading unit, an equalization unit, and a demodulation unit. The plurality of antennas receives radio signals transmitted from a plurality of the transmitting apparatuses. The signal storage unit stores reception signals received by each of the plurality of antennas. The reading unit reads, from the signal storage unit, reception signals including radio signals transmitted from a demodulation processing target transmitting apparatus, the reception signals being received by each of the plurality of antennas at different times. The equalization unit equalizes the plurality of reception signals read by the reading unit. The demodulation unit demodulates the equalized reception signals.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit, to a network node, a supported channel latency indication that indicates a supported channel latency for time domain equalization by the UE. The UE may receive, from the network node, a downlink communication based at least in part on the supported channel latency indication. Numerous other aspects are described.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit, to a network node, a supported channel latency indication that indicates a supported channel latency for time domain equalization by the UE. The UE may receive, from the network node, a downlink communication based at least in part on the supported channel latency indication. Numerous other aspects are described.

Integrated circuit devices, methods, and circuitry for linearity feedback to enable signal adjustment in multi-level signaling communication are provided. A system may include a first integrated circuit device with transmitter circuitry to controllably adjust levels of a multi-level signal and transmit the multi-level signal over a communication link. The system may also include a second integrated circuit device with receiver circuitry to receive the multi-level signal and instruct the transmitter circuitry to adjust the levels of the multi-level signal.

A system for an orthogonal frequency division multiplexed (OFDM) equalizer, said system comprising a program memory, a program sequencer and a processing unit connected to each other, wherein the processing unit comprises an input selection unit, an arithmetic logic unit (ALU), a coprocessor and an output selection unit; further wherein the program sequencer schedules the processing of one or more symbol-carrier pairs input to said OFDM equalizer using multiple threads; retrieves, for each of the one or more symbol-carrier pairs, multiple program instructions from said program memory; generates multiple expanded instructions corresponding to said retrieved multiple program instructions; and further wherein said ALU performs said processing of the one or more symbol-carrier pairs using the multiple threads across multiple pipeline stages, wherein said processing comprises said ALU executing arithmetic operations to process said expanded instructions using said multiple threads across the multiple pipeline stages.

Each transmitting apparatus transmits the same radio signals a plurality of times. A communication apparatus includes a plurality of antennas, a signal storage unit, a reading unit, an equalization unit, and a demodulation unit. The plurality of antennas receives radio signals transmitted from a plurality of the transmitting apparatuses. The signal storage unit stores reception signals received by each of the plurality of antennas. The reading unit reads, from the signal storage unit, reception signals including radio signals transmitted from a demodulation processing target transmitting apparatus, the reception signals being received by each of the plurality of antennas at different times. The equalization unit equalizes the plurality of reception signals read by the reading unit. The demodulation unit demodulates the equalized reception signals.

Provided is a method (300) and a successive interference cancellation (SIC) based multi-user uplink receiver (200) for multi-user uplink transmission. The method comprises receiving (302) signal of one or more multiple-access (MA) scheme waveforms by a plurality of antennas (202.1, . . . , 202.R) from one or more users. The method further comprises determining (304) one or more effective channel matrices corresponding to the plurality of antennas. Thereby, the method comprises performing (306) channel equalization for signal received in a corresponding antenna by an effective channel matrix. Furthermore, the method comprises combining (308) the channel equalized signal. Subsequently, the method comprises detecting (310) Correctly Decoded Code Blocks (CCBs) and Wrongly Decoded Code Blocks (WCBs). Upon detecting CCBs and WCBs, the method comprises performing (312) the SIC on received signals from one or more users until all WCBs are converted to CCBs or a maximum number of threshold iterations are completed.

An electronic device includes at least one antenna, and a channel estimation and equalization module for processing a reception signal received through the at least one antenna. The channel estimation and equalization module may identify the received signal and a reference signal related to the received signal. The channel estimation and equalization module may also, via deep learning based on the received signal and the reference signal: extract features of the received signal and the reference signal, estimate a channel of the received signal, based on the extracted features, and restore a signal corresponding to the received signal.