A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.

Methods and systems are described for receiving an input data voltage signal at a first data decision circuit of set of pipelined data decision circuits, receiving an aggregate decision feedback equalization (DFE) correction current signal from a first analog current summation bus, the aggregate DFE correction current signal comprising a plurality of DFE tap-weighted currents from respective other data decision circuits of the set of pipelined data decision circuits, determining a data output decision value based on the received input data voltage signal and the received aggregate DFE correction current signal, and generating at least one outbound DFE tap-weighted current on at least one other analog current summation bus connected to at least one other data decision circuit of the set of pipelined data decision circuits.

The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well.

The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well.

A transmitter equalization parameter evaluation method and an apparatus are provided. The method provided in this application is used for evaluating a transmitter equalization parameter of a high-speed interface in a first device, and the method is performed by a second device connected to the first device over a communication link. The second device first detects a status of the communication link between the first device and the second device, where the communication link is constructed through the high-speed interface in the first device. When determining that the communication link is idle, the second device performs a transmitter equalization parameter evaluation process of the high-speed interface in the first device based on the communication link. When the communication link is idle, the transmitter equalization parameter evaluation process of the high-speed interface in the first device is started. This ensures efficiency of transmitter equalization parameter evaluation.

A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.

Technologies for cooperative link equalization include a network device with a network interface controller (NIC). The NIC is to monitor variation in a property of a link channel that connects the network device with a target network device. The NIC detects, based on the channel variation, an event that triggers a condition to change an equalization setting of the link channel. In response to the detection, the NIC communicates, via an in-band equalization control channel, changes to the equalization setting of the link channel to the target network device.

The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well.

A decision feedback equalizer (DFE) may include a summer configured to receive a signal stream, and a plurality of feedback taps including a first feedback tap connected to the summer. The first feedback tap may include a pre-amplifier, a combined latch and a digital to analog converter (DAC). The pre-amplifier may be configured to be clocked by a first clock signal, wherein the pre-amplifier may be configured to receive an output signal of the summer and to receive a first postcursor generated by the DFE of a previous signal in the signal stream. The combined latch may be configured to be clocked by a first clock signal and a second clock signal. The DAC may be coupled to an output node of the combined latch. The first postcursor may be provided to the pre-amplifier without being provided to the summer.

A decision feedback equalizer (DFE) may include a summer configured to receive a signal stream, and a plurality of feedback taps including a first feedback tap connected to the summer. The first feedback tap may include a pre-amplifier, a combined latch and a digital to analog converter (DAC). The pre-amplifier may be configured to be clocked by a first clock signal, wherein the pre-amplifier may be configured to receive an output signal of the summer and to receive a first postcursor generated by the DFE of a previous signal in the signal stream. The combined latch may be configured to be clocked by a first clock signal and a second clock signal. The DAC may be coupled to an output node of the combined latch. The first postcursor may be provided to the pre-amplifier without being provided to the summer.