A method to implement hybrid signal processing includes steps for receiving an analog signal at a receiver frontend, sampling the received analog signal and storing the analog sampled signals using a plurality of sampling circuitries inside the receiver frontend. Then, processing the plurality of analog sampled signals using interleaved feed-forward equalizers (FFEs) to provide FFE interleaved sampled signal values corresponding to each of the sampling circuitries. Then, processing the analog sampled signals at an interleaved Decision Feedback Equalizer (DFE) to obtain DFE interleaved sampled signal values, summing each of the FFE interleaved sampled signal values with output from one of the DFE interleaved sampled signal values to provide equalizer output signal values, and digitizing the equalizer output signal values to provide digital data bits corresponding to each of the equalizer output signal values. Implementations of the method as a hybrid communication system, system-on-a-chip, and computer readable memory are also disclosed.

A method of equalizing a communication link includes setting a number of coefficients equal to a required number of coefficients, determining a number of pulse responses for a waveform, the number of pulse responses being greater than the number of coefficients, setting all values in a set of values to zero, the set of values having a number of values equal to the number of coefficients, repeating, until all values in the set of values have been assigned, determining a current lowest parameter in a set of given parameters, using a position of the current lowest parameter in the set of given parameters as an index, determining a minimum value between a first term in the set of given parameters multiplied by a main pulse response minus a summation of each parameter in the set of parameters multiplied by each value in the set of values, divided by the current lowest parameter, and a corresponding pulse response, and assigning the minimum value to the value in the set of values having a position equal to position of the current lowest parameter, and determining a value of each coefficient in a set of coefficients by multiplying each value in the set of values with the sign of a corresponding pulse response in the number of pulse responses; defining an equalizer having a number of taps equal to the number of coefficients, each tap having a value based on the corresponding coefficient; and applying the equalizer to a waveform received through the communication link to produce an equalized waveform. A test and measurement device is also disclosed.

Apparatus and associated methods relate to an ADC-based digital receiver including a feedforward equalizer (FFE) that has m precursor taps and n postcursor taps to equalize the precursor portion, and to adapt postcursor intersymbol interference (ISI) through a predetermined equalization coefficient selected to counteract the noise boosting effect associated with the precursor equalization. In an illustrative example, the receiver may dynamically balance noise and ISI through adaptively determining a coefficient hp.sub.1 of a first postcursor tap of a first FFE and a coefficient h.sub.1 of a first postcursor tap of a second equalizer adapted to substantially reduce or eliminate additional ISI introduced by the first FFE. The first FFE may optimize ISI removal and noise reduction, for example. One of the coefficients h.sub.1 and hp.sub.1 may be predetermined, and then the other coefficient may be iteratively adapted to trade off precursor ISI and postcursor ISI to minimize BER.

An information handling system includes a memory subsystem and a basic/input out system (BIOS). The BIOS performs multiple trainings of the memory subsystem, and each of the trainings is performed at a different temperature. The BIOS stores multiple derating values in a derating table of the BIOS, and each of the derating values corresponds to a respective tap value at a respective temperature. During a subsequent power on self test of the information handling system, the BIOS performs a first training of the memory subsystem, and stores a first set of tap values. During a runtime of the information handling system, a memory controller determines whether a temperature of the information handling system has changed by a predetermined amount. In response to the temperature changing by the predetermined amount, the memory controller utilizes the derating values in the derating table to automatically update the tap values.

The present disclosure proposes an adaptive non-speculative DFE with an extended time constraint for a PAM-4 receiver and a method for operating the same. An adaptive non-speculative DFE with an extended time constraint for a PAM-4 receiver according to the present disclosure comprises a Continuous-Time Linear Equalizer (CTLE) to boost high-frequency components of an input signal, a Track and Hold (T&H) circuit to track and hold an output of the CTLE, and a sampler, wherein the sampler includes a Decision Feedback Equalization (DFE) sampler to equalize an output of the T&H circuit and sample an output of the T&H circuit in a DFE sampling clock phase; and a DATA sampler to sample a signal equalized by the DFE sampler in a DATA sampling clock phase, wherein the DFE sampling clock phase differs from the DATA sampling clock phase.

A physical layer transceiver, for connecting a host device to a wireline channel medium having a cable length, includes a host interface for coupling to a host device, a line interface for coupling to the channel medium, and filter circuitry operatively coupled to the line interface. The filter circuitry includes a plurality of filter segments, fewer in number than a total number of link segments in the cable length. Individual filter segments in the plurality of filter segments are configurable to correspond to individual link segments, and are separately controllable from other filter segments. Control circuitry detects a change of transmission conditions in a particular link segment, and upon detection of the change of transmission conditions, changes a configuration of one of the plurality of filter segments to cause an alteration in filtering of signals in the particular link segment at which the change of transmission conditions is detected.

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.

A receiver converter circuit included in a computer system may receive multiple signals that encode a serial data stream that encode multiple data symbols. To correct for baseline wander, the receiver circuit may generate a disparity signal that is used to control the application of a differential voltage to the multiple signals. The receiver circuit may also employ the disparity signal to generate a gradient against which the magnitude of differential voltage is calibrated.

A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.