A device includes a receiver analog front-end circuit including a path shared by an internal loopback current path and a calibration current path, wherein the receiver analog front-end circuit is configured to perform an internal test using the internal loopback current path while in a test mode, and equalize a first data signal while in a normal mode, the equalizing the first data signal including removing an offset from the first data signal using the calibration current path.

According to an aspect, a data inversion circuit configured to perform DBI-AC encoding using a PAM 4 signal may comprise a data generation unit configured to generate input data based on the PAM 4 signal, a channel comprising N data lines, a first auxiliary signal generation unit configured to generate a first auxiliary signal that determines whether to perform a first encoding on the input data based on the number of each of a plurality of data symbols included in the input data, a first data encoding unit configured to generate intermediate data by performing the first encoding on the input data based on the first auxiliary signal, a second auxiliary signal generation unit configured to generate a second auxiliary signal that determines whether to perform a third encoding on the intermediate data by analyzing the relationship between a plurality of data symbols at a current time point and a plurality of data symbols at a previous time point included in the intermediate data and a second data encoding unit configured to generate encoded data by performing the third encoding on the intermediate data based on the second auxiliary signal, and to transmit the generated encoded data to a data reception unit via the channel and the first auxiliary signal and the second auxiliary signal may be combined into one signal and implemented as a PAM 4 signal.

Accordingly embodiments herein disclose a quarter rate speculative DFE. The quarter rate speculative DFE includes a plurality of sampler circuits connected to an input terminal. The plurality of sampler circuits are configured to sample an input signal into a plurality of data samples in parallel. A plurality of quarter rate look ahead circuit connected to the plurality of sampler circuits. The plurality of quarter rate look ahead circuit is configured to simultaneously perform an align operation and a look ahead operation on the plurality of data samples based on the different clock phases to obtain a plurality of latched outputs. A plurality of multiplexers connected to the plurality of quarter rate look ahead circuit. The plurality of multiplexers is configured to generate two speculative data streams by multiplexing respective correction coefficients of each of the plurality of latched outputs.

A multi-stage continuous time linear equalizer (CTLE) with a reconfigurable inductor scheme is disclosed. The multi-stage CTLE comprises a first stage transformer-based inductive peaking and a second stage resistive load. The first stage transformer-based inductive peaking is configured to control high frequency peaking and set a peak frequency value to a desired value by using a coarse equalization mechanism. The stage resistive load configured to provide tuneable equalization and low frequency fine equalization by using a fine equalization mechanism.

Disclosed are a clock and data recovery circuit, method and apparatus. The circuit comprises a receiving module for receiving an analog signal; a first equalization module connected to the receiving module, the first equalization module comprising a first totalizer and a second totalizer; a first sampling module connected to an output end of the first totalizer, the first sampling module comprising a first edge sampler and a second edge sampler that are connected to the output end of the first totalizer, respectively; a second sampling module connected to an output end of the second totalizer; a data processing module connected to both the first sampling module and the second sampling module; a clock recovery module connected to the data processing module; and an output module connected to the clock recovery module. In the present application, by means of the manner, a phase can be adjusted using a bias voltage, thereby accurately recovering clock information.

Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.

A system for selecting an equalizer setting of an equalizer to equalize signals received via a communications link. Starting with a first (e.g., minimum) equalizer setting and a threshold voltage near the mid-eye voltage of the equalized output signal, the system estimates the amplitude of the inner eye of the equalized output signal by comparing the equalized output signal to a series of threshold voltages. If the amplitude of the equalized output signal is less than ideal, the system dynamically increases the equalizer setting. The system quickly converges on the equalizer setting for the communication link because, rather than comparing the output signal at every voltage offset using every equalizer setting, the system only evaluates the equalizer settings necessary to select the equalizer setting for the communications link and uses only the voltage offsets necessary to evaluate each equalizer setting.

According to one embodiment, a semiconductor integrated circuit includes first and second power supply lines, first and second nodes, and first and second circuits. The first circuit is configured to supply a first current to the second power supply line, from the first node or the second node. The second circuit is configured to supply a second current from the first power supply line to the first node based on a magnitude of the first current, and to supply a third current from the first power supply line to the second node based on the magnitude of the first current.

An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.

An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.