Patent classifications
H04L25/03885
Data Reception Device
A data reception device includes: an equalizer circuit that shapes a waveform of an input signal according to a set gain value; a CDR circuit which recovers a plurality of clock signals having different phases in one cycle from the input signal after being subjected to the waveform shaping performed by the equalizer circuit; an oversampler which performs sampling of the waveform-shaped input signal in synchronization with the plurality of clock signals and recovers a plurality of input data from the waveform-shaped input signal; and a calibration control unit which determines whether the oversampler correctly recovers the input data based on a result of the sampling performed by the oversampler, and generates a control signal to set the gain value of the equalizer circuit based on a determination result when it is determined that the input data is not correctly recovered.
CONTINUOUS TIME LINEAR EQUALIZATION AND BANDWIDTH ADAPTATION USING PEAK DETECTOR
Methods and systems are described for asynchronously measuring an equalized information signal to obtain amplitude information, modifying frequency dependent parameters of a continuous-time linear equalization (CTLE) component of the signal path, determining a correlation between CTLE parameters and signal amplitude, and adjusting, responsive to the correlation, a continuous-time linear equalization (CTLE) code of a CTLE to adjust equalization of the equalized information signal.
Variable gain amplifier and sampler offset calibration without clock recovery
Methods and systems are described for generating a time-varying information signal at an output of a variable gain amplifier (VGA), sampling, using a sampler having a vertical decision threshold associated with a target signal amplitude, the time-varying information signal asynchronously to generate a sequence of decisions from varying sampling instants in sequential signaling intervals, the sequence of decisions comprising (i) positive decisions indicating the time-varying information signal is above the target signal amplitude and (ii) negative decisions indicating the time-varying information signal is below the target signal amplitude, accumulating a ratio of positive decisions to negative decisions, and generating a gain feedback control signal to adjust a gain setting of the VGA responsive to a mismatch of the accumulated ratio with respect to a target ratio.
Mitigation of multi-path interference from quasi-single-mode fiber using hybrid span configuration and digital signal processing
Aspects of the present disclosure are directed to the mitigation of multi-path interference from quasi-single-mode fiber using hybrid span configuration and digital signal processing wherein a hybrid span of quasi-single mode fibers and single-mode fibers are used to configure the hybrid span. Additional aspects are directed to introducing a low-baud rate sub-banding signal to reduce the number of DD-LMS taps required when compensating the multi-path interference as the low-baud rate signal requires fewer taps to cover a given range of MPI as compared to a high-baud rate signal. Finally further aspects are directed to an ALMS equalizer which further reduces the number of equalizer taps by shifting its center tap towards the right if higher-order modes transmit slower than a fundamental mode, otherwise the center tap is shifted to the left.
METHOD AND DEVICE FOR CONTROLLING A VECTOR PROCESSOR
In accordance with an embodiment the method includes temporarily configuring the vector processor with a new set of vectoring coefficients during one or more selected symbol positions; restoring the current set of vectoring coefficients outside the one or more selected symbol positions; obtaining at least one error measure over respectively at least one line of the group of vectored lines during the one or more selected symbol positions; and determining a suitability indication for the new set of vectoring coefficients based on the obtained at least one error measure.
CLOCK DATA RECOVERY WITH DECISION FEEDBACK EQUALIZATION
Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error indication, the phase error indication selected in response to identification of a predetermined data decision pattern.
Circuit for and method of receiving an input signal
A continuous time linear equalizer comprises an input of a first equalizer path configured to receive a first differential input signal; an input of a second equalizer path configured to receive a second differential input signal; a first programmable load capacitor coupled to an output of the first equalizer path; a second programmable load capacitor coupled to an output of the second equalizer path; and a programmable source capacitor coupled between the first equalizer path and the second equalizer path.
Built-in eye scan for ADC-based receiver
An example method of performing an eye-scan in a receiver includes: generating digital samples from an analog signal input to the receiver based on a sampling clock, the sampling clock phase-shifted with respect to a reference clock based on a phase interpolator (PI) code; equalizing the digital samples based on first equalization parameters of a plurality of equalization parameters of the receiver; adapting the plurality of equalization parameters and performing clock recovery based on the digital samples to generate the PI code; and performing a plurality of cycles of locking the plurality of equalization parameters, suspending phase detection in the clock recovery, offsetting the PI code, collecting an output of the receiver, resuming the phase detection in the clock recovery, and unlocking the equalization parameters to perform the eye scan.
Linear Equalization For Use In Low Latency High Speed Communication Systems
A communication system including a transmitter and a receiver is disclosed. The transmitter transmits frames, at least two consecutive frames containing different training sequences. The receiver receives data communicated from the transmitter over a channel. The receiver combines and jointly processes the at least two consecutive frames transmitted by the transmitter to estimate a channel state of the channel.
VOLTAGE CONTROLLED EQUALIZER NETWORK
An apparatus includes a radio frequency (RF) input port, an RF output port, a variable attenuation network, a first filter network, a second filter network, and a third filter network. The variable attenuation network may be coupled between the RF input port and the RF output port. Attenuation of the variable attenuation network is controlled by a first control signal and a second control signal. The first filter network may be connected between the RF input port and the RF output port. The second filter network may be connected between the variable attenuation network and a ground potential. The third filter network may be connected between the variable attenuation network and the ground potential. The first, the second, and the third filter networks modify performance of the variable attenuation network to produce a particular tilt of a radio frequency signal passing through the apparatus between the RF input port and the RF output port. The particular tilt is selectable by adjustment of at least one of the first and the second control signals.