Digital video signals are transmitted from a transmitter to a receiver via a digital video interface including shielded twisted pair cables that are surrounded by an over-braid shield. The over-braid shield is connected to a chassis ground at a transmitting end and the receiving end. An interface conveys the received signals to receiver processing circuitry. The interface is connected to an isolated ground, isolating the receiver processing circuitry. The twisted pairs are also connected to the isolated ground, such that a return current is forced back through the twisted pair cable shields rather than the over-braid shield. This reduces electromagnetic emissions and confines transients primarily to the over-braid shield.

Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.

Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between a transmitting device and a receiving device operating at high speed with low power utilization. Communication is performed using group signaling over sets of four wires using a vector signaling code, where each wire of a set carries a low-swing signal that may take on one of four signal values. Topologies and designs of wire sets are disclosed with preferred characteristics for group signaling communications.

Provided are a method and an apparatus for canceling interference, to resolve a problem that performance of interference cancellation is poor because accuracy of equalizer coefficients obtained by a CMTS through calculation is not sufficiently high. A specific solution is as follows: (101) A CMTS calculates L equalizer coefficients of an L-tap filter according to a preamble sequence by using an adaptive algorithm, and performs adaptive equalization on a received signal by using the L equalizer coefficients, where L is a positive integer greater than 24; and (102) the CMTS selects K equalizer coefficients from the L equalizer coefficients, and sends a ranging response message carrying the K equalizer coefficients to a cable modem CM, so that the CM performs pre-equalization on a to-be-sent signal according to the received K equalizer coefficients, where K is a positive integer less than or equal to L.

An apparatus for performing fractionally spaced adaptive equalization with non-integer sub-symbol sampling has an adaptive equalizer that receives a continuous stream of input data having a non-integer, fractional delay between consecutive samples at a non-integer, sub-symbol rate and outputs a stream of equalized data based on tap weights of taps of the adaptive equalizer that are spaced at an interval corresponding to the non-integer, sub-symbol rate. The tap weights are updated independently of the fractional delay between consecutive samples of the input data using an error signal. An equalizer output alignment component downstream of the adaptive equalizer aligns the stream of equalized data with a corresponding transmitted symbol.

An apparatus for processing data includes a linear equalizer, a load switchably connected to an output of the linear equalizer, a slicer configured to sample a signal derived from the output of the linear equalizer, and a detector circuit configured to detect an over-equalization condition in data to be sampled by the slicer and to connect the load to the output of the linear equalizer in the over-equalization condition.

An example automatic gain control (AGC) circuit includes a base current-gain circuit having a programmable source degeneration resistance responsive to first bits of an AGC code word. The AGC circuit further includes a programmable current-gain circuit, coupled between an input and an output of the base current-gain circuit, having a programmable current source responsive to second bits of the AGC code word. The AGC circuit further includes a bleeder circuit, coupled to the output of the base current-gain circuit, having a programmable current source responsive to logical complements of the second bits of the AGC code word. The AGC circuit further includes a load circuit coupled to the output of the base current-gain circuit.

A predistortion method and apparatus are provided which use a DPD actuator (225) to apply a memory polynomial formed with first DPD coefficients to a first input signal x[n], thereby generating a first pre-distorted input signal y[n] which is provided to the non-linear electronic device (253) to produce the output signal, where the memory polynomial may be adaptively modified with a digital predistortion adapter (224) which computes second DPD coefficients u[n] with an iterative fixed-point conjugate gradient method which uses N received digital samples of the first pre-distorted input signal y[n] and a feedback signal z[n] captured from the output signal to process a set of conjugate gradient parameters (u, b, v, r, ω, α, β) at each predetermined interval, thereby updating the first DPD coefficients with the second DPD coefficients u[n] generate a second pre-distorted input signal which is provided to the non-linear electronic device.

A decision feedback equalizer includes a positive signal line, a negative signal line, a sense amplifier, a feedback driver, a load unit, a differential driver, and a charge pump. The differential driver maintains a difference between the first voltage of the positive signal line and the second voltage of the negative signal line at a last time point of the normal period to be equal to or greater than the reference voltage by adjusting strength of the positive input current corresponding to a positive input signal and strength of the negative input current corresponding to a negative input signal based on a temperature signal. The charge pump provides a positive offset voltage and a negative offset voltage to the positive signal line and the negative signal line, respectively. The positive offset voltage and the negative offset voltage are used to maintain an average voltage of the first voltage and the second voltage at the last time point of the normal period at a first value.

An apparatus includes a decision feedback equalizer configured to receive a parallel signal generated based on a first clock. The decision feedback equalizer includes a first equalization block configured to receive a first symbol of a first set of parallel symbols provided by the parallel signal during a first clock cycle of the first clock. A decision feedback equalization is performed by the first equalization block to the first symbol to provide a first decision to a second equalization block. The second equalization block is configured to receive a second symbol of the first set of parallel symbols and perform a decision feedback equalization to the second symbol using the first decision received from the first equalization block to provide a second decision during the first clock cycle.