A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.

A system and a method for detecting a low-frequency periodic signal (LFPS) include at least one comparator performing a threshold comparison on an analog input signal over a period of time. A sampling circuit generates digital signals by sampling an output of the at least one comparator. A digital detection circuit applies a set of detection rules to the digital signals. The detection rules are configured to detect a presence or an absence of an LFPS based on predefined criteria concerning characteristics of the digital signals.

A serial data receiver subsystem of a computer system includes a data rate detection circuit and a receiver circuit. The data rate detection circuit is configured to detect that a communication link operates in a high-speed mode rather than in a low-speed mode by detecting that a number of transitions in a serial data stream over a reference period of time exceeds a threshold value. The date rate detection circuit is further configured to activate a data rate detection signal indicating that the communication link operates in the high-speed mode, the data rate detection signal activated in response to detection that the number of transitions in the serial data stream over the reference period of time exceeds the threshold value. The receiver circuit is configured to activate one or more of a plurality of subcircuits included in the receiver circuit in response to activation of the data rate detection signal.

A signal transmission method includes receiving, by a controller, a request signal sent by a first transmitter. The method includes establishing, by the controller according to the request signal, a second optical path that connects the first transmitter to the second receiver in the optical switching network (OSN). The method includes sending, by the controller, to the second receiver according to the request signal, a reset signal used to instruct the second receiver to be reset to an initial state. The method includes sending, by the controller, an acknowledgement signal to the first transmitter. The acknowledgment signal is used to instruct the first transmitter to send, by using the second optical path, an optical signal to the second receiver.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Systems and methods related for duo-binary transceivers with adaptive channel equalization are described. An example method for adapting a channel between a first duo-binary transceiver and a second duo-binary transceiver, different from the first duo-binary transceiver, where the transmitter includes a feed-forward equalizer (FFE), is described. The method includes, at a receiver associated with the second duo-binary transceiver, selectively processing information at a given time from only an upper eye or a lower eye of a received duo-binary signal to determine updated coefficients for the feed-forward equalizer (FFE) of the transmitter associated with the first duo-binary transceiver. The method further includes using a backchannel between the transmitter and the receiver, sending the updated coefficients to the transmitter. The method further includes transmitting duo-binary signals that are equalized using the updated coefficients for the FFE of the transmitter associated with the first duo-binary transceiver.

A system and method are disclosed to extract the sequence of symbols of a digitally modulated signal, which jointly recover the symbol synchronism, equalize the transmission channel and mitigate interfering signals. In addition, an algorithm is disclosed to adaptively update the response of finite impulse response filters which recursively computes the filter taps every N samples of the input signal, where N is the ratio between the symbol rate and the sampling rate.

A feed forward equalizer includes a plurality of delay circuits connected to each other in series and configured to delay input signals. A plurality of filters respectively correspond to outputs of the plurality of delay circuits, except for a reference output which is an output of a first delay circuit among the plurality of delay circuits, and the input signals. A calculator configured to sum the reference output and outputs of the plurality of filters. Each of the plurality of filters is configured to receive an output of a delay circuit corresponding thereto, among the plurality of filters, and the reference output.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Noise caused by and leaking from a transmit signal into a radio-frequency (RF) receive path signal is reduced by forwarding the transmit signal to a first filter or a digital processor and DAC, scaling the transmit signal and approximating the noise, subtracting first and second corrective signals from the RF receive path signal, down-converting a resulting corrected RF receive path signal, filtering the down-converted corrected signal in a second filter, up-converting the filtered corrected signal to create the first corrective signal, and up-converting the filter or DAC output signal to create the second corrective signal. The transmit signal may come from an output of an RF power amplifier, and may be down-converted prior to filtering in the first filter or processing in the digital processor. The second filter may be a series filter or a shunt filter. A radio includes the circuits to perform the above method.