Methods and systems are described for obtaining a plurality of BER-specific correction values by comparing a first set of BER values obtained by sampling, at a sampling instant near the center of a signaling interval, a non-DFE corrected received signal with a second set of BER values obtained by sampling a DFE-corrected received signal at the sampling instant. A set of eye-scope BER measurements are obtained, each eye-scope BER measurement having a sampling offset relative to the sampling instant, a voltage offset value representing a voltage offset applied to alter a decision threshold, and an eye-scope BER value. A set of DFE-adjusted eye-scope BER measurements are generated by using BER-specific correction values to adjust the voltage offset values of the eye-scope BER measurements.

A system includes a data carrier drive apparatus and a data carrier apparatus. The data carrier apparatus includes: an unit configured to output transmission data during a first state and adjustment data during a second state; and a current changer configured to change a current value of a current flowing from the data carrier drive apparatus to the data carrier apparatus according to data values of the transmission data and the adjustment data. The data carrier drive apparatus includes: a detector configured to detect a detection value corresponding to the current value of the current; a determiner configured to determine the data value of the transmission data by comparing the detection value with a threshold value during the first state; and an updater configured to update the threshold value based on the detection value during the second state.

The disclosed embodiments provide a system that implements a low-aperture-delay sampler. The system includes a sampler input, which receives an input signal, and a clock input, which receives a clock signal. The system also includes: a first sampling channel, which samples the input signal when the clock signal is low and is associated with a previous clock phase; and a second sampling channel, which samples the input signal when a rising edge is received in the clock signal, wherein the rising edge is associated with a present clock phase. The system additionally includes a combining mechanism, which combines outputs of the first and second sampling channels to produce a sampler output with a significantly reduced aperture delay.

The disclosed embodiments provide a system that implements a low-aperture-delay sampler. The system includes a sampler input, which receives an input signal, and a clock input, which receives a clock signal. The system also includes: a first sampling channel, which samples the input signal when the clock signal is low and is associated with a previous clock phase; and a second sampling channel, which samples the input signal when a rising edge is received in the clock signal, wherein the rising edge is associated with a present clock phase. The system additionally includes a combining mechanism, which combines outputs of the first and second sampling channels to produce a sampler output with a significantly reduced aperture delay.

Methods and systems are described for obtaining a plurality of BER-specific correction values by comparing a first set of BER values obtained by sampling, at a sampling instant near the center of a signaling interval, a non-DFE corrected received signal with a second set of BER values obtained by sampling a DFE-corrected received signal at the sampling instant. A set of eye-scope BER measurements are obtained, each eye-scope BER measurement having a sampling offset relative to the sampling instant, a voltage offset value representing a voltage offset applied to alter a decision threshold, and an eye-scope BER value. A set of DFE-adjusted eye-scope BER measurements are generated by using BER-specific correction values to adjust the voltage offset values of the eye-scope BER measurements.

Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

A system and method for data sampler drift compensation in a SerDes receiver. Off-data values are received at a drift compensation engine from a plurality of data value selectors coupled to one of a plurality of data sampler pairs of a speculative Decision Feedback Equalizer (DFE) of a SerDes receiver. A drift compensation value for each of the data samplers is generated by the drift compensation engine based upon the off-data values received from each of the plurality of data value selectors and, a sampling level of each of the data samplers of the plurality of data sampler pairs of the DFE is adjusted based upon the drift compensation value from the drift compensation engine.

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.