A method and system are provided for drift compensation, providing a live data approach to sampler offset calibration, such as for voltage and/or temperature (VT) drift. A serializer/deserializer (SerDes) system includes a SerDes receiver and receiver logic, the receiver logic including a forward error correction (FEC) module. A drift compensation device, or drift compensation engine, receives live error corrections from the FEC module based on FEC operations performed on live traffic passing through the SerDes receiver. A drift compensation command is provided to a data sampler in the SerDes receiver, to adjust a sampling voltage of the data sampler. When the system includes a plurality of data samplers, the drift compensation device determines the data sampler with which an error correction is associated. The drift compensation command can be sent after a threshold criterion is satisfied, such as completion of a statistics collection period, or a threshold number of corrections.

The present disclosure relates to a user equipment (200) for a wireless communication system. The user equipment comprises a transmitter (210) configured to generate a transmit signal (220), a transmitter feedback receiver (230) coupled to the transmitter and configured to measure a power of the transmit signal in a first mode of operation, and control circuitry (240) configured to select a second mode of operation of the transmitter feedback receiver, in which the transmitter feedback receiver (230) is configured to measure one or more neighboring inter-frequency or inter-RAT base stations.

Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

Methods and systems are described for obtaining a plurality of BER-specific correction values by comparing a first set of BER values obtained by sampling, at a sampling instant near the center of a signaling interval, a non-DFE corrected received signal with a second set of BER values obtained by sampling a DFE-corrected received signal at the sampling instant. A set of eye-scope BER measurements are obtained, each eye-scope BER measurement having a sampling offset relative to the sampling instant, a voltage offset value representing a voltage offset applied to alter a decision threshold, and an eye-scope BER value. A set of DFE-adjusted eye-scope BER measurements are generated by using BER-specific correction values to adjust the voltage offset values of the eye-scope BER measurements.

An access point may include a radio. The radio may receive a waveform, and the waveform may comprise a plurality of pulses. The access point may further include a hardware processor coupled to the radio. The hardware processor may determine a model of the received waveform. Determining a model of the received waveform may include extracting a plurality of characteristics corresponding to the received waveform, determining a plurality of parameters, wherein each of the plurality of parameters is based on a corresponding characteristic of the plurality of characteristics, and constructing an output waveform model based on the plurality of parameters, wherein the output waveform model corresponds to the received waveform. The hardware processor may further transmit the output waveform model to the hardware processor as an input waveform, wherein the input waveform is to tune the model. Moreover, the access point may include a dynamic frequency switching (DFS) module coupled to the hardware processor to receive the output waveform model.

A radio receiver, configured to use an impulse UWB, includes: a reception antenna which receives the impulse UWB, a reception unit which amplifies the received impulse UWB and detects an envelope of the impulse UWB, maximum-peak and minimum-peak detection units which detect a maximum value and minimum value of the envelope, respectively, a comparator which acquires signal data from the envelope with an initial threshold value, a baseband unit which measures an error rate of the signal data, an MPU which calculates a correction value based on the error rate, and an arithmetic unit which calculates a corrected threshold value based on the maximum, minimum and correction values. The arithmetic unit transmits the corrected threshold value to the comparator. The comparator acquires the signal data from the envelope based on the corrected threshold value transmitted from the arithmetic unit.

Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

An access point may include a radio. The radio may receive a waveform, and the waveform may comprise a plurality of pulses. The access point may further include a hardware processor coupled to the radio. The hardware processor may determine a model of the received waveform. Determining a model of the received waveform may include extracting a plurality of characteristics corresponding to the received waveform, determining a plurality of parameters, wherein each of the plurality of parameters is based on a corresponding characteristic of the plurality of characteristics, and constructing an output waveform model based on the plurality of parameters, wherein the output waveform model corresponds to the received waveform. The hardware processor may further transmit the output waveform model to the hardware processor as an input waveform, wherein the input waveform is to tune the model. Moreover, the access point may include a dynamic frequency switching (DFS) module coupled to the hardware processor to receive the output waveform model.

An EHF receiver that determines an initial slicing voltage level and dynamically adjusts the slicing voltage level and/or amplifier gain levels to account for characteristics of the received EHF electromagnetic data signal. The architecture includes an amplifier, detector, adaptive signal slicer, and controller. The detector includes a main detector and replica detector that convert the received EHF electromagnetic data signal into a baseband signal and a reference signal. The controller uses the baseband signal and reference signal to determine an initial slicing voltage level, and dynamically adjust the slicing voltage level and the gain settings of the amplifier to compensate for changing signal conditions.

An apparatus is described that includes a receiver. The receive includes a data sampler, a positive error sampler and a negative error sampler each having respective inputs coupled to a same differential channel. The receiver also includes circuitry to drive the respective inputs, the circuitry to place a same calibration voltage on the differential channel to calibrate each of the data sampler, positive error sampler and negative error sampler with the same calibration voltage.