Methods, systems are provided for reconfiguring the position of a first tap in a descrambler circuit LFSR after the LFSR has been trained and synchronized with a corresponding scrambler circuit LFSR. A data path from the second tap position to the descrambler output by-passes logic elements located in the data path from the first tap to the descrambler output, thereby reducing delay in the descrambler circuit after the reconfiguration (i.e., the “lock-shift” operation). The tap position change may be communicated by a mode manager to a corresponding scrambler circuit, for applying a matching reconfiguration in the scrambler circuit, either directly via an I/O line or indirectly. The indirect route includes in-band transmissions between two ICs with two sets of self-synchronizing scrambler/descrambler pairs, and is based on monitored receiver LFSR output signals that indicate when a scrambler/descrambler pair is synchronized or whether the output of a descrambler circuit comprises descrambled data.

A data transmission interface for use in a first integrated circuit, for encoding and sending a data packet from the first IC to a second IC via a data bus having three data wires, the data transmission interface being arranged to generate three time-dependent binary signals which jointly encode the data packet, each of the signals being associated with a unique data wire of the data bus and spanning a temporal cycle T within which are defined six consecutive time stamps T.sub.1 . . . T.sub.6 at which the signals are allowed to change logical state, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein, irrespective of the data packet content: at each time stamp T.sub.1 . . . T.sub.6 exactly one of the signals changes logical state; each signal changes logical state twice during the cycle; and in the first half of the cycle, all signals change from a logical low state to a logical high state or all signals change from a logical high state to a logical low state.

A power transmitter includes: a first switch coupled between a first node and a reference voltage node; a second switch configured to be coupled between a power supply and the first node; a coil and a capacitor coupled in series between the first node and the reference voltage node; a first sample-and-hold (S&H) circuit having an input coupled to the first node; and a timing control circuit configured to generate a first control signal, a second control signal, and a third control signal that have a same frequency, where the first control signal is configured to turn ON and OFF the first switch alternately, the second control signal is configured to turn ON and OFF the second switch alternately, and where the third control signal determines a sampling time of the first S&H circuit and has a first pre-determined delay from a first edge of the first control signal.

A method for transmitting a data block begins with segmenting the data block into a number of data sub-blocks. Each data sub-block where a number of high bits is greater than a number of low bits is then inverted. The data sub-blocks are then grouped into sets of data sub-blocks. For each set of data sub blocks, a number of pulses indicative of a number of high bits in each one of the data sub-blocks in the set is transmitted, there is a delay, and a number of pulses indicative of each high bit in each data sub-block of the set of data sub-blocks is transmitted followed by a delay. Finally, a number of pulses indicative of which ones of the data sub-blocks were inverted is transmitted.

A method of encoding a stream of data bits includes encoding a bit 1 of the data stream as a first symbol if a bit immediately preceding the bit 1 is encoded as 0 and a bit of the data stream immediately succeeding the bit 1 is 0, encoding the bit immediately succeeding the bit 1 as 1, encoding a bit 0 of the data stream as a second symbol if a bit immediately preceding the bit 0 is encoded as 1 and a bit of the data stream immediately succeeding the bit 0 is 1, and encoding the bit immediately succeeding the bit 0 as 0.

Embodiments of a method and a device are disclosed. In an embodiment, a method for operating a wired communications device involves including a frame boundary bit sequence and a random data sequence as a preamble of a bit stream, encoding the bit stream into an encoded bit stream, and transmitting the encoded bit stream using the wired communications device.

A repeater includes a reception unit, a permission signal generating unit that detects the state of the pulses of the signal, and generates a permission signal that permits a relay of the signal when the permission signal generating unit detects the pulses, and that inhibits the relay of the signal when the permission signal generating unit detects an end of the pulses, and a transmission unit. When detecting the end of the pulses, for the permission signal, the permission signal generating unit sets a pulse re-input monitoring period for determining whether or not the pulses of the signal are re-detected. When detecting the pulses of the signal during the pulse re-input monitoring period, the permission signal generating unit determines that the signal continues, and when not detecting the pulses of the signal, the permission signal generating units determines that the signal ends.

An illustrative SerDes (serializer-deserializer) communications method embodiment may include a transceiver: selecting one of multiple registers to specify initial pre-equalizer coefficient values; updating the initial pre-equalizer coefficient values during a training phase; and using the updated pre-equalizer coefficient values to convey a transmit data stream. In an illustrative embodiment of a chip-to-module communications link, a port connector couples a port transceiver to a pluggable module transceiver, the pluggable module transceiver including: one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to the port transceiver; and a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values, the controller using one of the registers to set initial coefficient values for the one or more transmit filters.

Methods and apparatuses are provided for transmitting and receiving a signal using a sequence in a wireless communication system. The method includes receiving, from a base station, information indicating whether sequence hopping is applied or not; transmitting, to the base station, the signal using a first sequence if a number of resource blocks allocated to the user equipment is less than a predetermined value; and transmitting, to the base station, the signal using a second sequence to which the sequence hopping is applied based on the received information if the number of the resource blocks allocated to the user equipment is greater than or equal to the predetermined value. The sequence hopping is performed using a pseudo-random function, and the sequence hopping is performed in a unit of a slot.

A system comprising a rack and at least one line replaceable module, the rack further comprising a primary transmission circuit comprising a primary antenna, primary emission components designed to generate an emitted power containing uplink data, and primary receiving components designed to receive downlink data, the line replaceable module comprising a secondary transmission circuit comprising a secondary antenna, secondary receiving components designed to receive the emitted power and the uplink data, and secondary emission components designed to generate the downlink data, the emitted power, the uplink data and the downlink data being transmitted via a shared coupling between the primary antenna and the secondary antenna.