Using a transformation based at least in part on a non-simple orthogonal or unitary matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. Hybrid transformers that apply such transformations to selected subsets of signals to be transmitted may be used to adapt to various signal set sizes and/or transmission environment properties including noise and physical space requirements of given transmission environments.

A system includes a first encoder configured to receive first input bits and generate a first stream of first bits based on the first input bits, a bit generator configured to receive second inputs bits and generate a second stream of second bits based on the second input bits, and a PAM4 transmitter configured to receive the first stream of first bits and the second stream of second bits, and generate PAM4 symbols based at least on the first stream of first bits.

A transceiver includes a duobinary conversion circuit configured to determine a level of an input signal which is a duobinary signal according to an intermediate voltage, a first reference voltage higher than the intermediate voltage, and a second reference voltage lower than the intermediate voltage, and to convert the input signal into a non-return-to-zero (NRZ) signal; and a control circuit configured to generate one or more control signals to substantially remove inter-symbol interference (ISI) between symbols of the input signal, and to adjust the first reference voltage, or the second reference voltage, or both according to the level of the input signal.

A device and method for a receiver configured to perform timing recovery decoupled feed-forward equalizer (FFE) adaptation. The receiver device can include an analog front-end (AFE) device, which is coupled to a time-interleaved (TI) interface. The TI interface is coupled in a timing recovery feedback loop to FFE equalizers, a digital signal processor (DSP), a delay timing loop (DTL) device, and a clock device, which feeds back to the TI interface. The DSP has an additional pathway to the FFE equalizers, which has an additional pathway to the DTL device. The DTL loop is equipped with an interleave specific enable/disable vector Q[1:N] that can turn on/off the contribution of the specific time interleave errors to the timing recovery loop, which allows the FFE adaptation process to be decoupled from the timing recovery loop.

A system and method for efficiently transferring data between devices. In various embodiments, a host computing device receives parallel data, encodes the parallel data as a count of pulses as serial data, and conveys the serial data to a peripheral device. The peripheral device decodes the received serial data to determine the parallel data, which is sent to processing logic. The devices send the encoded pluses on a bidirectional line, so the pulses are capable of being sent in both directions. The devices send the encoded pulses on the bidirectional line using a non-zero base voltage level. The devices are capable of using a voltage headroom when conveying encoded pulses between one another. Therefore, a full voltage swing between a ground reference voltage level and a power supply voltage level is not used when conveying the encoded pulses, which reduces power consumption.

A device and method for a receiver configured to perform timing recovery decoupled feed-forward equalizer (FFE) adaptation. The receiver device can include an analog front-end (AFE) device, which is coupled to a time-interleaved (TI) interface. The TI interface is coupled in a timing recovery feedback loop to FFE equalizers, a digital signal processor (DSP), a delay timing loop (DTL) device, and a clock device, which feeds back to the TI interface. The DSP has an additional pathway to the FFE equalizers, which has an additional pathway to the DTL device. The DTL loop is equipped with an interleave specific enable/disable vector Q[1:N] that can turn on/off the contribution of the specific time interleave errors to the timing recovery loop, which allows the FFE adaptation process to be decoupled from the timing recovery loop.

A system and method for recovering encoded data from a modulated baseband signal is disclosed. Aspects and embodiments of the system and method include receiving an analog input signal representing a modulated baseband signal, counting clock cycles of a reference clock, detecting a first transition and a second transition of the analog input signal indicating a first change and a second change in the modulated baseband signal, storing a first counter value corresponding to an amount of clock cycles elapsed between the first transition and the second transition, and determining a binary-valued bit sequence corresponding to the first counter value.

The present solution provides a signal processing device, including: an encoder which encodes second transmitting data by referring to first transmitting data which is previously transmitted and the second transmitting data which is a current transmitting target such that at least one bit signal of the second transmitting data has a binary level different from that of a corresponding bit signal of the first transmitting data; and a transmitter which sequentially transmits the first transmitting data and the second transmitting data.

Provided is a precoding method for generating, from a plurality of baseband signals, a plurality of precoded signals to be transmitted over the same frequency bandwidth at the same time, including the steps of selecting a matrix F[i] from among N matrices, which define precoding performed on the plurality of baseband signals, while switching between the N matrices, i being an integer from 0 to N−1, and N being an integer at least two, generating a first precoded signal z1 and a second precoded signal z2, generating a first encoded block and a second encoded block using a predetermined error correction block encoding method, generating a baseband signal with M symbols from the first encoded block and a baseband signal with M symbols the second encoded block, and precoding a combination of the generated baseband signals to generate a precoded signal having M slots.

Using a transformation based at least in part on a non-simple orthogonal or unitary matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. Hybrid transformers that apply such transformations to selected subsets of signals to be transmitted may be used to adapt to various signal set sizes and/or transmission environment properties including noise and physical space requirements of given transmission environments.