A transmitter (TX)-side feedforward equalizer (FFE) includes one or more “roaming” filter taps which can be used to compensate reflections that occur at unpredictable and substantial time offsets from a main pulse. The roaming filter taps are realized in a hardware- and power-efficient manner by implementing a programmable delay serializer in which the phases of multi-rate clocks are switched to introduce binary weighted delays on the roaming tap. In this way a variable difference in latencies is introduced between the main and the roaming tap data paths. The TX-side FFE implementations provide a fully programmable roaming tap generator having a 1-Unit Interval (UI) resolution of delay setting integrated into the data serializer of the TX macro.

A data transmission interface for use in a first integrated circuit, for encoding and sending a data packet from the first IC to a second IC via a data bus having three data wires, the data transmission interface being arranged to generate three time-dependent binary signals which jointly encode the data packet, each of the signals being associated with a unique data wire of the data bus and spanning a temporal cycle T within which are defined six consecutive time stamps T.sub.1 . . . T.sub.6 at which the signals are allowed to change logical state, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein, irrespective of the data packet content: at each time stamp T.sub.1 . . . T.sub.6 exactly one of the signals changes logical state; each signal changes logical state twice during the cycle; and in the first half of the cycle, all signals change from a logical low state to a logical high state or all signals change from a logical high state to a logical low state.

There is disclosed integrated circuitry comprising having a bit receiving arrangement adapted for receiving, in parallel, a plurality of data bits, the bit receiving arrangement further being adapted for receiving a data bit inversion bit associated to the plurality of data bits, the data bit inversion bit being for indicating whether the bits of the plurality of data bits are inverted. The integrated circuitry also comprises has a bit inversion arrangement adapted for inverting the bits of the plurality of data bits based on a comparison between the received data bit inversion bit and an inversion estimate bit, the inversion estimate bit being determined based on the plurality of data bits. The disclosure also pertains to related methods and devices.

Using a transformation based at least in part on a non-simple orthogonal or unitary matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. Hybrid transformers that apply such transformations to selected subsets of signals to be transmitted may be used to adapt to various signal set sizes and/or transmission environment properties including noise and physical space requirements of given transmission environments.

This application relates to an encoding method and apparatus, and a display apparatus. The encoding method includes encoding 8-bit data corresponding to a to-be-encoded byte of to-be-transmitted data into alternative 10-bit data, the to-be-transmitted data including at least one to-be-encoded byte, detecting whether the first-digit data of the alternative 10-bit data is the same as the previous-digit data adjacent to the first-digit data, when the to-be-encoded byte is not the first byte of the to-be-transmitted data, inverting the alternative 10-bit data to obtain target 10-bit data, when the numerical value of the first-digit data is the same as that of the previous-digit data, and determining the alternative 10-bit data as the target 10-bit data, when the numerical value of the first-digit data is different from that of the previous-digit data. The 8-bit data, the alternative 10-bit data and the target 10-bit data are binary data.

A transceiver includes a duobinary conversion circuit configured to determine a level of an input signal which is a duobinary signal according to an intermediate voltage, a first reference voltage higher than the intermediate voltage, and a second reference voltage lower than the intermediate voltage, and to convert the input signal into a non-return-to-zero (NRZ) signal; and a control circuit configured to generate one or more control signals to substantially remove inter-symbol interference (ISI) between symbols of the input signal, and to adjust the first reference voltage, or the second reference voltage, or both according to the level of the input signal.

Provided is a precoding method for generating, from a plurality of baseband signals, a plurality of precoded signals to be transmitted over the same frequency bandwidth at the same time, including the steps of selecting a matrix F[i] from among N matrices, which define precoding performed on the plurality of baseband signals, while switching between the N matrices, i being an integer from 0 to N−1, and N being an integer at least two, generating a first precoded signal z1 and a second precoded signal z2, generating a first encoded block and a second encoded block using a predetermined error correction block encoding method, generating a baseband signal with M symbols from the first encoded block and a baseband signal with M symbols the second encoded block, and precoding a combination of the generated baseband signals to generate a precoded signal having M slots.

This application relates to an encoding method and apparatus, and a display apparatus. The encoding method includes encoding 8-bit data corresponding to a to-be-encoded byte of to-be-transmitted data into alternative 10-bit data, the to-be-transmitted data including at least one to-be-encoded byte, detecting whether the first-digit data of the alternative 10-bit data is the same as the previous-digit data adjacent to the first-digit data, when the to-be-encoded byte is not the first byte of the to-be-transmitted data, inverting the alternative 10-bit data to obtain target 10-bit data, when the numerical value of the first-digit data is the same as that of the previous-digit data, and determining the alternative 10-bit data as the target 10-bit data, when the numerical value of the first-digit data is different from that of the previous-digit data. The 8-bit data, the alternative 10-bit data and the target 10-bit data are binary data.

Using a transformation based at least in part on a non-simple orthogonal or unitary matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. Hybrid transformers that apply such transformations to selected subsets of signals to be transmitted may be used to adapt to various signal set sizes and/or transmission environment properties including noise and physical space requirements of given transmission environments.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.