H04L25/4917

Memory devices configured to generate pulse amplitude modulation-based DQ signals, memory controllers, and memory systems including the memory devices and the memory controllers

A memory device as provided may apply a pulse amplitude modulation method to data (DQ) signal transmission/reception and may scale a DQ signal according to an operating frequency condition, so as to improve data transmission performance and effectively improve power consumption. The memory device includes a memory cell array, and a data input/output circuit configured to scale a DQ signal that includes data read from the memory cell array and output the scaled DQ signal. The data input/output circuit is configured to scale the DQ signal based on an n-level pulse amplitude modulation (PAMn) (where n is 4 or a greater integer) with a DQ parameter that corresponds an operating frequency condition and output the DQ signal. Other aspects include memory controllers that communicate with the memory devices, and memory systems that include the memory devices and memory controllers.

MASKED TRAINING AND ANALYSIS WITH A MEMORY ARRAY
20220350512 · 2022-11-03 ·

Methods, systems, and devices for masked training and analysis with a memory array are described. A memory device may operate in a first mode in which a maximum transition avoidance (MTA) decoder for a memory array of the memory device is disabled. During the first mode, the memory device may couple an input node of the MTA decoder with a first output node of a first decoder, such as a first pulse amplitude modulation (PAM) decoder. The memory device may operate in a second mode in which the MTA decoder for the memory array is enabled. During the second mode, the memory device may couple the input node of the MTA decoder with a second output node of a second decoder, such as a second PAM decoder.

CMOS SIGNALING FRONT END FOR EXTRA SHORT REACH LINKS
20220353115 · 2022-11-03 · ·

A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.

Multi-level coded modulation for non-coherent communication

Disclosed are techniques related to wireless communication system in which multi-level encoded modulation (MLCM) is applied to non-coherent communication. In the proposed techniques, a small fraction of differential phase rotations or bits participating in differential symbol coding are protected with strong codes while other complementary differential phase rotations or bits are protected with weaker codes. Compared to conventional non-coherent communication techniques in which a uniform protection is applied to any fraction of differential phase rotation or any bit of a differential symbol, the proposed MLCM approach enables more spectrally efficient scheme.

ULTRA-HIGH-SPEED PAM-N CMOS INVERTER SERIAL LINK

Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

SYSTEMS AND METHODS FOR TRANSITION ENCODING COMPATIBLE PAM4 ENCODING
20230081418 · 2023-03-16 ·

A system includes a first encoder configured to receive first input bits and generate a first stream of first bits based on the first input bits, a bit generator configured to receive second inputs bits and generate a second stream of second bits based on the second input bits, and a PAM4 transmitter configured to receive the first stream of first bits and the second stream of second bits, and generate PAM4 symbols based at least on the first stream of first bits.

Optical transceiver design for short distance communication systems based on microLEDs

MicroLEDs may be used for short-range optical communications. Signal equalization may be used to decrease distortion in transmitted and/or received information, including with the use of multi-level modulation formats.

MULTILEVEL CODING FOR PHYSICAL LAYER SECURITY

Methods, systems, and devices for wireless communications are described. In a multilevel encoding scheme, a transmitting device may divide a stream of information bits in a message into multiple substreams, and the transmitting device may input each substream to a different level of an encoder such that each substream is encoded separately. The transmitting device may also input excess bits to some levels of the encoder to add physical layer security to the message. To improve the chances that a receiving device is able to correctly decode the message, the receiving device may be configured to identify the levels at which the excess bits are encoded. Accordingly, the receiving device may be able to decode the information bits in the message and avoid attempting to decode the excess bits in the message as information bits.

Method to vertically align multi-level cell
11606229 · 2023-03-14 · ·

Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify vertical alignment between data transmitted using multi-level signaling. Such multi-level signaling may be configured to capture transmitted data during a single clock cycle of a memory controller. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

MULTI-LEVEL SIGNAL TRANSMITTER AND METHOD THEREOF
20220337458 · 2022-10-20 ·

A multi-level signal transmitter includes an encoder figured to receive an input data and output a plurality of logical signal sets, each of said plurality of logical signal sets comprising a plurality of logical signals; and a plurality of tree-structured drivers configured to receive said plurality of logical signal sets, respectively, and jointly establish an output voltage at an output node, wherein each of said tree-structure drivers comprises a plurality of inverters configured to receive said plurality of logical signals of its respective logical signal set and jointly establish a joint voltage at a bifurcation node via coupling to the bifurcation node through a plurality of first-level weighting resistors, and a second-level weighting resistor configured to couple the bifurcation node to the output node.