H04L25/493

TRANSMITTER AND COMMUNICATION SYSTEM
20170288920 · 2017-10-05 · ·

A transmitter according to the disclosure includes: three first driver sections; three first pre-driver sections that are provided corresponding to the respective three first driver sections, and each drive corresponding one of the first driver sections on a basis of corresponding one of three first control signals that are different from one another and each including predetermined number of signals; a second pre-driver section that operates on a basis of a second control signal that includes predetermined number of signals; and a controller that controls transition of the predetermined number of signals included in the second control signal to allow number of signals to be subjected to the transition out of the plurality of signals included in the three first control signals and the plurality of signals included in the second control signal to be same between timings of the transition.

SOUNDWIRE XL TURNAROUND SIGNALING
20170250794 · 2017-08-31 ·

System, methods and apparatus are described that improve link turnaround performance in a differentially driven link. A method performed at a first device coupled to a two-wire serial link includes transmitting from the first device first differentially-encoded data to a second device over the two-wire serial link during a first time period, receiving at the first device second differentially-encoded data from the second device over the two-wire serial link during a second time period, and driving by the first device both wires of the two-wire serial link to a common voltage level during a third time period, the third time period spanning a link turnaround period between the first time period and the second time period. Both wires of the two-wire serial link are driven toward the common voltage level by the second device during the third time period.

Matrix phase interpolator for phase locked loop
11245402 · 2022-02-08 · ·

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

Matrix phase interpolator for phase locked loop
11245402 · 2022-02-08 · ·

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

Modulating signal level transitions to increase data throughput over communication channels

An encoder for modulating data on level transitions of a signal transmitted on a wired communication channel to increase channel data throughput, comprising a circuitry configured for receiving a signal transmitted by a transmitting communication node, the signal carries a message to one or more receiving communication nodes connected to a wired communication channel, calculating a respective delay period consisting of a number of delay time units encoding one or more data items, delaying one or more transitions of a waveform level of the signal by the respective delay period to modulate the signal to carry the data item(s) and transmitting the modulated signal to one or more of the receiving communication nodes having a decoder configured for demodulating the modulated signal.

Modulating signal level transitions to increase data throughput over communication channels

An encoder for modulating data on level transitions of a signal transmitted on a wired communication channel to increase channel data throughput, comprising a circuitry configured for receiving a signal transmitted by a transmitting communication node, the signal carries a message to one or more receiving communication nodes connected to a wired communication channel, calculating a respective delay period consisting of a number of delay time units encoding one or more data items, delaying one or more transitions of a waveform level of the signal by the respective delay period to modulate the signal to carry the data item(s) and transmitting the modulated signal to one or more of the receiving communication nodes having a decoder configured for demodulating the modulated signal.

EVENT-DRIVEN TRANSMISSION METHOD AND DEVICE
20210407261 · 2021-12-30 ·

An event-driven transmission method comprises converting at least one event to at least one corresponding pulse pair and transmitting the at least one pulse pair. In this context, a delay between each pulse pair represents a corresponding identifier with respect to the respective event or with respect to at least one corresponding object causing or experiencing the respective event.

DATA-DRIVEN PHASE DETECTOR ELEMENT FOR PHASE LOCKED LOOPS
20220166434 · 2022-05-26 ·

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

DATA-DRIVEN PHASE DETECTOR ELEMENT FOR PHASE LOCKED LOOPS
20220166434 · 2022-05-26 ·

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

C-PHY HALF-RATE WIRE STATE ENCODER AND DECODER
20220158879 · 2022-05-19 ·

Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.