Embodiments of a method and a device are disclosed. In an embodiment, a method for operating a wired communications device involves performing a bit mapping operation on an input bit stream to generate a mapped bit stream, performing a bit scrambling operation in response to the mapped bit stream to generate a scrambled bit stream, generating an encoded bit stream in response to the scrambled bit stream, and transmitting the encoded bit stream using the wired communications device.

A transmission device of the disclosure includes: a plurality of delay sections having changeable delay amounts; a driver section that includes a plurality of drivers and transmits a data signal indicating a sequence of symbols using the plurality of drivers, the plurality of drivers being provided to correspond to the plurality of delay sections and setting a voltage at a corresponding output terminal to a mutually different voltage on the basis of a signal delayed by a corresponding delay section of the plurality of delay sections; and a controller that sets the respective delay amounts of the plurality of delay sections on the basis of a transition of a symbol in the sequence of symbols.

A method for a bus interface circuit is described. According to one exemplary embodiment, the method comprises coding a first data stream by assigning first symbols to falling and rising edges of the first data stream, and coding a further data stream by assigning second symbols to the edges or levels of said further data stream. A symbol sequence is constructed from the first symbols and second symbols, wherein said symbol sequence is constructed in such a manner that the first symbols are always delayed by the same value relative to the associated edges of the first data stream. The method also comprises transmitting the symbol sequence via a galvanically isolating component, and decoding the symbol sequence transmitted via the galvanically isolating component in order to reconstruct the first data stream and the further data stream.

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.

Methods and systems are described for receiving, at a data-driven phase comparator circuit, a plurality of data signals in parallel and one or more phases of a local oscillator signal, the data-driven phase comparator circuit comprising a plurality of partial phase comparators, generating a plurality of partial phase-error signals using the partial phase comparators, each partial phase-error signal generated by receiving (i) a corresponding phase of the local oscillator signal and (ii) a corresponding data signal of the plurality of data signals and responsive to a determination that a transition occurred in the corresponding data signal, generating the partial phase-error signal based on a comparison of the corresponding phase of the local oscillator signal and the corresponding data signal, and generating a composite phase-error signal by summing the plurality of partial phase error signals for setting a local oscillator in a lock condition.

Methods and systems are described for generating, with a local oscillator and an adjustable phase interpolator, a data-sampling clock and a variable-phase-offset eye-measurement clock, forming a received data signal using a multi-input comparator, generating, using a data slicer and the data sampling clock, a receive sample of the received data signal, and generating, using at least one eye slicer and the variable-phase-offset eye-measurement clock, a plurality of eye characteristic measurements by adjusting a sampling threshold of the at least one eye slicer and a phase offset of the variable-phase-offset eye-measurement clock.

Methods and systems are described for generating, with a local oscillator and an adjustable phase interpolator, a data-sampling clock and a variable-phase-offset eye-measurement clock, forming a received data signal using a multi-input comparator, generating, using a data slicer and the data sampling clock, a receive sample of the received data signal, and generating, using at least one eye slicer and the variable-phase-offset eye-measurement clock, a plurality of eye characteristic measurements by adjusting a sampling threshold of the at least one eye slicer and a phase offset of the variable-phase-offset eye-measurement clock.

A signal transmission circuit which transmits N (N is a natural number of 2 or more) input signals includes a transmission signal generation portion, 2.sup.N transmission portions and an output portion. The transmission signal generation portion generates 2.sup.N transmission signals according to the N input signals. The 2.sup.N transmission portions respectively transmit the 2.sup.N transmission signals output from the transmission signal generation portion while performing electrical insulation. The output portion generates and outputs, based on the 2.sup.N transmission signals transmitted by the 2.sup.N transmission portions, N output signals that respectively indicate the N input signals. The transmission signal generation portion generates a pulse according to the N input signals and incorporates the pulse in only one of the 2.sup.N transmission signals at the same time.

A signal transmission circuit which transmits N (N is a natural number of 2 or more) input signals includes a transmission signal generation portion, 2.sup.N transmission portions and an output portion. The transmission signal generation portion generates 2.sup.N transmission signals according to the N input signals. The 2.sup.N transmission portions respectively transmit the 2.sup.N transmission signals output from the transmission signal generation portion while performing electrical insulation. The output portion generates and outputs, based on the 2.sup.N transmission signals transmitted by the 2.sup.N transmission portions, N output signals that respectively indicate the N input signals. The transmission signal generation portion generates a pulse according to the N input signals and incorporates the pulse in only one of the 2.sup.N transmission signals at the same time.