A carrier generator includes a phase accumulator configured to generate a phase reference signal based on a frequency command word (FCW) signal, a time to digital converter (TDC) configured to generate a feedback signal based on a divided signal, a loop filter configured to generate a filtered command signal based on the phase reference signal and the feedback signal, and a plurality of tuning arrangements. Each tuning arrangement includes an oscillator configured to receive the filtered command signal and output an adjustment signal, and is configured to output a carrier signal of a corresponding plurality of carrier signals based on the adjustment signal. The divided signal is based on the adjustment signal of a first tuning arrangement.

A method for demodulating a signal is provided. The method includes: acquiring a reference clock signal provided by a power management unit (PMU) in a mobile terminal; determining a moving velocity of the mobile terminal; determining, based on the moving velocity, a Doppler frequency shift value generated when the mobile terminal receives a radio frequency (RF) signal transmitted by a base station; and demodulating, according to the reference clock signal and the Doppler frequency shift value, the received RF signal.

An apparatus for detecting the end of a communication is disclosed. The apparatus includes an interface circuit for receiving an encoded signal and a carrier signal recovery circuit coupled to an output of the interface circuit. The carrier signal recovery circuit is configured to output a carrier signal of the encoded signal and a second signal that is out of phase with the carrier signal. The apparatus also includes a decoding circuit configured to decode the encoded signal as a function of both the encoded signal and the carrier signal output by the carrier signal recovery circuit. The apparatus also includes a detection circuit configured to detect an indication of an end of a communication in the encoded signal as a function of both the encoded signal and the second signal.

A method for operating an RFID device is disclosed. In the embodiment, the method involves establishing a radio-frequency link, receiving signal samples of the radio-frequency link, determining the offset of an initial phase of the link by filtering noise from the signal samples, windowing the filtered signal samples, and calculating an offset value from phase differences between the windows of signal samples, and modifying a configuration profile based on the offset value. During data transmission the configuration profile can be used to configure the transmitter in order to maintain the constant phase during transmission.

An embodiment of the present invention relates to an ultra low power wideband asynchronous binary phase shift keying (BPSK) demodulation method and a circuit configuration thereof. The ultra low power wideband asynchronous BPSK demodulation circuit comprises a sideband division and upper sideband signal delay unit dividing a modulated signal into an upper sideband and a lower sideband by a first order high-pass filter and a first order low-pass filter; a data demodulation unit latching, through a hysteresis circuit, a signal generated by a difference between the analog signals in which a phase difference between the delayed upper sideband analog signal and the lower sideband analog signal is aligned at 0, so as to demodulate digital data; and a data clock recovery unit for generating a data clock by using a signal digitalized from the lower sideband analog signal through a comparator and a data signal.

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

A carrier generator includes a phase accumulator configured to receive a frequency command word (FCW) signal. The carrier generator includes an adder connected to the phase accumulator; and a loop filter configured to receive an output of the adder. The carrier generator includes a plurality of tuning arrangements, each tuning arrangement is configured to receive an output of the loop filter. Each tuning arrangement includes an electronic oscillator configured to receive the output of the loop filter. Each tuning arrangement includes a voltage controlled delay line (VCDL) configured to receive an output of the electronic oscillator, and to provide a tuning arrangement output. Each tuning arrangement includes a phase detector configured to receive a corresponding recovered clock signal and a feedback from a corresponding tuning arrangement output. Each tuning arrangement includes a counter configured to receive an output of the phase detector and to provide an output to the VCDL.

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

In an embodiment, a circuit includes a synchronizer configured to generate a trigger signal synchronized to a reference clock. A synthesizer is configured to synthesize a signal according to frequency control data in response to the trigger signal. A radio receiver is configured to process a carrier signal according to the synthesized signal. A phase measurement unit is configured to measure a first channel frequency response based on the processed carrier signal.

Methods and systems for synchronizing at least one remote local oscillator with a central local oscillator, comprising receiving a remote local oscillator signal from at least one remote local oscillator and a master local oscillator signal from the central local oscillator and in response determining a round-trip phase measurement of temporal delay variability of the duplex real-time link between the remote station and central station, measuring frequency vs. time of the remote local oscillator signal relative to the master oscillator, adjusting the measured frequency vs. time according to the round-trip phase measurement to remove effects of temporal delay variability over the duplex real-time link telemetry, digitally filtering the measured frequency to remove variations in frequency on timescales<10 the round-trip delay and that are known not to be intrinsically due to the remote local oscillator, generating a phase increment signal from the filtered measured frequency, receiving and adjusting the local oscillator signal according to the phase increment signal and in response generating a derived digital domain clock signal that tracks the master local oscillator signal and converting the derived digital domain clock signal to an ultra-low phase-noise time domain voltage clock signal.