A circuit for demodulating an input signal is described. The circuit may be configured to demodulate signals modulated with amplitude-based modulation schemes, such as amplitude shift keying (ASK), such that information is encoded in the amplitude of the signals. The circuit may comprise an amplitude detector for extracting the envelope of a received amplitude-modulated signal, a phase/frequency detector for detecting phase and/or frequency shifts, and a selector configured to select one between the output of the amplitude detector and the output of the phase/frequency detector. The selector may be controlled by a control circuit including a delay unit.

A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.

A user equipment (UE) for channel estimation in a high-speed single-frequency network (HS-SFN) is provided. The UE includes at least one non-transitory computer-readable medium; and at least one processor, which, when executing instructions stored on the at least one non-transitory computer-readable medium, causes the UE to perform a method including calculating an estimated frequency offset (FO) correction for a received signal using at least an FO estimation generated by an automatic frequency control (AFC) module using at least a previously-calculated channel estimate output from a channel estimator (CE) as input in a first feedback loop; and calculating, by the CE, a current channel estimate using at least the received signal adjusted by the estimated FO correction from the first feedback loop and one or more channel parameter estimates generated by the AFC using at least the previously-calculated channel estimate output from the CE as input in a second feedback loop.

A robust frequency drift tracking receiver. The received signal is translated to an intermediate frequency in the RF stage by a quadrature demodulator, and is then brought into the base band by a digital mixer made by a CORDIC. A base band processing stage allows for a synchronization of the receiver relative to the data frame, to estimate data and to output a counter-reaction signal to the CORDIC, obtained by integration of successive frequency corrections, with a predetermined step.

Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

A transceiver may include a reception (Rx) radio frequency (RF) part configured to process a received signal, a transmission (Tx) RF part configured to process a transmitted signal, and a phase lock loop (PLL) configured to provide a reception frequency to the reception RF part and provide a transmission frequency to the transmission RF part. The PLL may be controlled according to whether the reception RF part or the transmission RF part is on. In addition, a transceiver may include quenching waveform generator (QWGs) to control quenching waveforms of the RF parts corresponding to a plurality of antennas. The quenching waveforms may be generated respectively by VCOs operating at a same frequency. The QWGs may control the VCOs such that the quenching waveforms do not overlap.

A modulator operable to control an oscillator is described. The modulator can include a memory that stores oscillator control values and a bit streaming block. The bit streaming block can generate a bit stream based on the oscillator control values and transmit the bit stream to the oscillator to control an oscillation frequency of the oscillator. The modulator can also include a bit streaming loader (BSL). The BSL can receive one or more of the oscillator control values from the memory, generate one or more corresponding bit values based on the one or more of the oscillator control values, and provide the one or more bit values to the bit streaming block. The bit streaming block can then generate the bit stream based the one or more bit values generated by the BSL.

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

Systems and methods for transpositional modulation and demodulation are provided. One such method for generating a signal includes the steps of providing a look-up table having a plurality of quarter-cycle waveforms, each of said quarter-cycle waveforms associated with a respective input level; receiving an input signal; and outputting quarter-cycle waveforms associated with levels of the received input signal. Systems for transpositional modulation are also provided. One such system for generating a signal includes a look-up table having a plurality of quarter-cycle waveforms. Each of the quarter-cycle waveforms are associated with a respective input level, and the look-up table is configured to receive an input signal, and output quarter-cycle waveforms associated with levels of the received input signal.

Apparatuses (and methods of manufacturing same), systems, and methods for channel interpolation/estimation and/or frequency tracking suitable for a receiver in a high speed single frequency network (HS-SFN) scenario are described. In one aspect, an estimated frequency offset (FO) correction is calculated for a received signal using at least an FO estimation provided by an automatic frequency control (AFC) in a first feedback loop and a channel estimate is calculated using at least the estimated FO and one or more channel parameter estimates from the AFC in a second feedback loop. In another aspect, a phase locked loop (PLL) receives an lth orthogonal frequency division multiplexing (OFDM) symbol and produces a per-tap phase value for each tap i of the lth OFDM symbol. The per-tap phase values of the lth OFDM symbol are used to generate the PLL output, which is also used as input to a feedback loop.