A method and system for performing a duty cycle correction and quadrature error correction for a quarter-rate architecture TX/RX communication system, including correcting a duty cycle error between a first clock signal and a second clock signal, and correcting a quadrature error between a third clock signal and a fourth clock signal.

The present disclosure discloses a method and a device for extracting broadband error calibration parameters, and a computer-readable storage medium. The method includes: performing frequency band splitting on link broadband signals of an ultra-wide band system according to a received frequency band index table to generate sub-bands; extracting an amplitude error and a phase error of each sub-band; and iteratively weighting and accumulating, according to the frequency band index table and a preset broadband weight table, the amplitude error and the phase error of each sub-band one by one to an initial amplitude error compensation parameter and an initial phase error compensation parameter respectively, to synthesize and extract broadband error calibration parameters.

An apparatus includes a radio frequency (RF) receiver. The RF receiver includes a timing correlator and frequency offset estimator. The timing correlator and frequency offset estimator: (a) extracts timing from a set of samples derived from an RF signal, and (b) determines a frequency offset estimate from the set of samples.

A circuit for processing Carrier Aggregation (CA) is provided. The circuit includes a plurality of Component Carrier (CC) processors, each CC processor configured to estimate a frequency offset for a related CC and to compensate the estimated frequency offset, a reference clock generator configured to generate a reference clock using a reference frequency offset as one of frequency offsets output from the plurality of CC processors, a plurality of reception Phase Lock Loop (PLL) units, each reception PLL unit configured to generate a reception carrier frequency for the related CC corresponding to the reference clock, and a plurality of transmission PLL units, each transmission PLL unit configured to generate a transmission carrier frequency for the related CC corresponding to the reference clock.

A Bluetooth receiver is provided. The Bluetooth receiver comprises processing circuitry configured to receive a receive signal and to determine receive symbols based on the receive signal. The Bluetooth receiver further comprises control circuitry configured to determine a frequency offset and/or a modulation index of the receive signal based on the receive signal. The control circuitry is additionally configured to control an operation mode of the processing circuitry based on the determined frequency offset and/or the modulation index of the receive signal.

A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.

On-chip spread spectrum characterization including obtaining, from a skitter circuit, skitter data comprising a spread width corresponding to an amplitude of a spread of a spread spectrum clock signal; setting an offset pointer to a center of the spread width corresponding to the amplitude of the spread; retrieving, for each of a number of reference clock cycles, edge data indicating a location, within the spread width, of an edge of the spread spectrum during the reference clock cycle; incrementing, using the edge data, an offset counter for each reference clock cycle during which the edge of the spread spectrum crosses the offset pointer; and calculating a frequency of the spread spectrum using the offset counter and the number of reference clock cycles.

An apparatus and method for carrier frequency estimation include a carrier frequency estimator having: a frequency input terminal disposed to receive a frequency-domain input signal comprising a plurality of symbols; a plurality of candidate pipelines, each comprising a frequency adder coupled to the frequency input terminal, a bit converter coupled to the frequency adder, a multi-bit buffer coupled to the bit converter; and a correlator coupled to the multi-bit buffer, respectively; and a candidate pipeline selector coupled to the correlators.

A modulation format estimation device 100 includes: a frequency shift correction unit 112 configured to estimate the amount of a frequency shift using a baseband signal acquired from a received signal and correct the baseband signal based on an estimation result; a frequency error generation unit 122 configured to generate a plurality of frequency errors from a range set based on an error occurring in the estimation of the frequency shift amount; a frequency error introduction unit 123 configured to acquire learning baseband signals in which each of a plurality of source signals modulated by different modulation formats is frequency-shifted by each frequency error; and a modulation format estimation unit 113 configured to input a corrected baseband signal to a first machine learning model created by machine learning using learning data including the plurality of learning baseband signals and a label, and estimate a modulation format of the received signal.

The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). A method of determining a frequency-domain offset parameter of a preamble in a random access channel and a corresponding user equipment (UE) is provided. The method includes obtaining a random access channel subcarrier spacing Δf.sub.RA, a preamble length L.sub.RA and a uplink (UL) channel subcarrier spacing Δf from a base station and determining a frequency-domain offset parameter k of a preamble in a random access channel based on the obtained random access channel subcarrier spacing Δf.sub.RA, preamble length L.sub.RA and UL channel subcarrier spacing Δf . Other embodiments of the disclosure further provide a random access method, a method for configuring random access information and related device, and a corresponding computer readable medium.