Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

A carrier frequency offset (CFO) tracking circuit includes: a CFO estimation circuit, generating an estimated CFO signal; a loop filter, coupled to the CFO estimation circuit, performing a loop filter operation on the estimated CFO signal according to an initial value to generate a loop filtered result; and an averaging circuit, coupled to the CFO estimation circuit and the loop filter, performing an average operation on the estimated CFO signal to generate the initial value as an average of the estimated CFO signal.

An automatic frequency control (AFC) device is provided. The AFC device includes an input module, a received signal strength indicator (RSSI) module and a carrier frequency offset (CFO) estimation module. The input module down converts and samples a received signal. The RSSI module is coupled to the input module and calculates a RSSI signal in response to the down converted and sampled received signal. The CFO estimation module is coupled to the input module and the RSSI module and calculates a moving average of binary elements of the down converted and sampled received signal. The CFO estimation module continues to calculate the moving average until the AFC converges.

Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

A transceiver includes a transmission module for generating an output signal, a controller for controlling the transmission module to allow an output signal to have one of a first frequency and a second frequency, a reception module for controlling the controller to allow a control signal to be outputted based on completion information received from the outside. The transmission module outputs an output signal having a first frequency to perform human body communication. When the reception module receives completion information, the transmission module outputs an output signal having a second frequency in response to the control signal in order to perform wireless communication. The first frequency is lower than the second frequency.

The present disclosure provides a symbol synchronization method and apparatus. By means of the symbol synchronization method and apparatus, a timing location is adjusted outside an adaptive loop. In addition, the adaptive loop proceeds to according to an original function of the adaptive loop. That is, the timing location is stabilized to an initial symbol-synchronization location, and the timing location is then further corrected and adjusted. Therefore, impact of an error of a timing location on symbol synchronization is eliminated by correcting the timing location, and positioning accuracy of a symbol-synchronization location is improved.

A technique uses linear prediction to determine the location of spurious content in a digital phase-locked loop and suppresses the spurious content from propagating to the clock output. In at least one embodiment, the technique implements an iterative (e.g., recursive) computation.

A transceiver includes a transmission module for generating an output signal, a controller for controlling the transmission module to allow an output signal to have one of a first frequency and a second frequency, a reception module for controlling the controller to allow a control signal to be outputted based on completion information received from the outside. The transmission module outputs an output signal having a first frequency to perform human body communication. When the reception module receives completion information, the transmission module outputs an output signal having a second frequency in response to the control signal in order to perform wireless communication. The first frequency is lower than the second frequency.

A circuit includes a frequency generation circuit having a phase locked loop, PLL, arranged to generate a carrier frequency; and a controller operably coupled to the frequency generation circuit and arranged to determine a frequency location of one or more signals output by the frequency generation circuit and provide a control signal thereto to adjust the carrier frequency generated by the frequency generation circuit. The controller is arranged to: cooperate with the PLL to introduce a frequency offset in the generated carrier frequency in a first frequency direction; and introduce a compensating frequency offset in a baseband transmit signal in a second frequency direction opposite to the first frequency direction.