A variety of methods, systems, devices and arrangements are implemented for assessing and/or controlling call routing for Internet-based (e.g., VoIP/VioIP) calls. According to one such method, endpoint devices are used to monitor and/or assess the call-quality. The assessment is sent to a centralized server arrangement and call-routing is controlled therefrom. Endpoint devices employ a decentralized testing mechanism to further monitor and assess call quality including the use of test connections. Aspects of call quality are analyzed and attributed to endpoint devices and/or local connections or networks to distinguish intermediate routing issues from local/endpoint issues.

A high-speed digital transmitter for wireless communication systems includes a plurality of transmitter chain circuits configured to respectively receive incoming component signals having a first frequency and to produce outgoing transmission signals having a second frequency greater than the first frequency in a first domain. In some aspects, the incoming component signals are up-sampled to the second frequency using a plurality of streams processed concurrently at a predetermined sample rate over a predetermined number of interpolation filter stages in each of the plurality of transmitter chain circuits. The high-speed digital transmitter also includes a serializer configured to combine the outgoing transmission signals from the plurality of transmitter chain circuits into a serialized transmission signal having a third frequency greater than the second frequency in a second domain different from the first domain.

A method for operating a data processing system to compute the response of a DUT to a modulated input signal is disclosed. The method includes determining a set of parameters for a first model of the DUT from a plurality of measurements of output values from the DUT, each output value includes a measurement of a gain and phase shift provided by the DUT when the DUT is stimulated with a single tone input signal having a frequency in a frequency range determined by the modulated signal. The method also determines a second model that characterizes noise generated by the DUT at the single tone input signals. A performance parameter for an output signal that would be obtained by applying the modulated input signal to an input of the DUT, and receiving the output of the DUT is then determined from the first and second models.

A receiver module includes a clock recovery circuit and a decision feedback equalizer (DFE) circuit. The DFE circuit includes a data feedback loop configured to sample an input data stream combined with equalization values based on a first clock signal. The DFE circuit also includes an edge feedback loop configured to sample the input data stream combined with equalization values based on a second clock signal. The clock recovery circuit is configured to determine a phase error between a receiver clock signal and a target clock signal based on output samples from the data feedback loop and the edge feedback loop.

This disclosure relates to data communication networks. An example data communication apparatus includes physical (PHY) layer circuitry that includes transceiver circuitry, decoder circuitry, and a signal analysis unit. The transceiver circuitry receives encoded data symbols via a network link. The received encoded data symbols are encoded using trellis coded modulation (TCM). The decoder circuitry decodes the received encoded data symbols using maximum-likelihood (ML) decoding to map a received symbol sequence to an allowed symbol sequence using a trace-back depth. A trace-back depth value is a number of symbols in the received symbol sequence used by the ML decoding to identify the allowed symbol sequence from the received symbol sequence. The signal analysis unit determines one or more link statistics of the network link, and sets the trace-back depth value according to the one or more link statistics.

This disclosure relates to data communication networks. An example data communication apparatus includes physical (PHY) layer circuitry that includes transceiver circuitry, decoder circuitry, and a signal analysis unit. The transceiver circuitry receives encoded data symbols via a network link. The received encoded data symbols are encoded using trellis coded modulation (TCM). The decoder circuitry decodes the received encoded data symbols using maximum-likelihood (ML) decoding to map a received symbol sequence to an allowed symbol sequence using a trace-back depth. A trace-back depth value is a number of symbols in the received symbol sequence used by the ML decoding to identify the allowed symbol sequence from the received symbol sequence. The signal analysis unit determines one or more link statistics of the network link, and sets the trace-back depth value according to the one or more link statistics.

According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

This application discloses a computing system to perform a fast evaluation of a worst case eye diagram for a channel capable of communicating signals encoding data in more than two value levels. The computing system can identify multiple step responses of the channel, each corresponding to a transition between a plurality of the value levels. The computing system can determine distribution boundaries of the signals at each of the value levels based, at least in part, on the step responses of the channel. The computing system can utilize the distribution boundaries at the value levels to determine boundaries of eye openings between adjacent value levels or to build worst case input patterns used to generate the worst case eye diagram for the channel. The computing system can predict a signal integrity of the channel based on the distribution boundaries at each of the value levels.

According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

Methods and apparatus for processing multichannel signals in a multichannel receiver are described. In one implementation, a plurality of demodulators may provide a plurality of outputs to a processor, with the processor then simultaneously estimating noise characteristics based on the plurality of outputs and generating a common noise estimate based on the plurality of outputs. This common noise estimate may then be provided back to the demodulators and used to adjust the demodulation of signals in the plurality of demodulators to improve phase noise performance.