Patent classifications
H04L27/152
Receive device, recording medium for receiving signal
A quadrature detector subjects a received signal to quadrature detection and outputs a base band signal. A direct current component measurement circuit measures a magnitude of a direct current component included in the base band signal from the quadrature detector. A first HPF and a second HPF reduce the direct current component included in the base band signal from the quadrature detector. A demodulator demodulates the base band signal output from the first HPF and the second HPF. A controller exercises control to attenuate a level of the received signal input to the quadrature detector when the magnitude of the direct current component measured by the direct current component measurement circuit is equal to or larger than a threshold value.
HALF-DUPLEX USER EQUIPMENT OPERATION IN NEW RADIO FREQUENCY DIVISION DUPLEXED BANDS
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine a guard period associated with switching from a first communication mode to a second communication mode. The UE may be operating in a half-duplex frequency division duplexing mode of operation. The guard period may be determined based at least in part on at least one of: a number of phased locked loops to be used for the first communication mode and the second communication mode, and a particular subcarrier spacing associated with the UE. The UE may switch from the first communication mode to the second communication mode based at least in part on the guard period. Numerous other aspects are provided.
Phase error reduction in a receiver
A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.
Methods and apparatus for wideband and fast chirp generation for radar systems
Methods, apparatus, systems and articles of manufacture for wideband and fast chirp generation for radar systems are disclosed herein. An example apparatus includes a phase digital-to-analog converter to convert a digital input that specifies at least one of a phase modulation or a frequency modulation into an analog output, and to generate a phase modulated output centered on an intermediate frequency. The example apparatus also includes a frequency multiplier to frequency multiply the phase modulated output centered on the intermediate frequency by a multiplication factor to generate a chirp signal.
Systems and methods for frequency domain local oscillator frequency offset compensation
The disclosed systems and methods for frequency domain (FD) local oscillator frequency offset (LOFO) compensation. The method comprising: i) compensating, by an integer Fast Fourier Transform (FFT) bins-based oscillator, LOFO in a received signal by an integer number of FFT bins; and ii) compensating, by a fractional FFT bins-based oscillator, LOFO in the compensated signal by the integer FFT bins-based oscillator with a fine compensation resolution of a fractional number of FFT bins.
Systems and methods for frequency domain local oscillator frequency offset compensation
The disclosed systems and methods for frequency domain (FD) local oscillator frequency offset (LOFO) compensation. The method comprising: i) compensating, by an integer Fast Fourier Transform (FFT) bins-based oscillator, LOFO in a received signal by an integer number of FFT bins; and ii) compensating, by a fractional FFT bins-based oscillator, LOFO in the compensated signal by the integer FFT bins-based oscillator with a fine compensation resolution of a fractional number of FFT bins.
RF-powered micromechanical clock generator
A microelectromechanical resonant switch (resoswitch) converts received radio frequency (RF) energy into a clock output. The resoswitch first accepts incoming amplitude- or frequency-shift keyed clock-modulated RF energy at a carrier frequency, filters it, provides power gain via resonant impact switching, and finally envelop detects impact impulses to demodulate and recover the carrier clock waveform. The resulting output derives from the clock signal that originally modulated the RF carrier, resulting in a local clock that shares its originator's accuracy. A bare push-pull 1-kHz RF-powered mechanical clock generator driving an on-chip inverter gate capacitance of 5 fF can potentially operate with only 5 pW of battery power, 200,000 times lower than a typical real-time clock. Using an off-chip inverter with 17.5 pF of effective capacitance, a 1-kHz push-pull resonator would consume 17.5 nW.
RF-powered micromechanical clock generator
A microelectromechanical resonant switch (resoswitch) converts received radio frequency (RF) energy into a clock output. The resoswitch first accepts incoming amplitude- or frequency-shift keyed clock-modulated RF energy at a carrier frequency, filters it, provides power gain via resonant impact switching, and finally envelop detects impact impulses to demodulate and recover the carrier clock waveform. The resulting output derives from the clock signal that originally modulated the RF carrier, resulting in a local clock that shares its originator's accuracy. A bare push-pull 1-kHz RF-powered mechanical clock generator driving an on-chip inverter gate capacitance of 5 fF can potentially operate with only 5 pW of battery power, 200,000 times lower than a typical real-time clock. Using an off-chip inverter with 17.5 pF of effective capacitance, a 1-kHz push-pull resonator would consume 17.5 nW.
Phase locked loop frequency shift keying demodulator using an auxiliary charge pump and a differential slicer
Various embodiments relate to a PLL based FSK demodulator, the FSK demodulator comprising a PFD configured to receive an input signal, a fully differential auxiliary charge pump configured to receive and amplify the input signal from the PFD, a capacitor configured to filter the input signal from the auxiliary charge pump and a fully differential slicer configured to demodulate the input signal and output recovered data.
Phase locked loop frequency shift keying demodulator using an auxiliary charge pump and a differential slicer
Various embodiments relate to a PLL based FSK demodulator, the FSK demodulator comprising a PFD configured to receive an input signal, a fully differential auxiliary charge pump configured to receive and amplify the input signal from the PFD, a capacitor configured to filter the input signal from the auxiliary charge pump and a fully differential slicer configured to demodulate the input signal and output recovered data.