A mixer is connected to a signal generator and an antenna and outputs a signal at an intermediate frequency. A PLL demodulator subjects the signal at the intermediate frequency from the mixer to PLL demodulation. An amplifier amplifies a signal from the PLL demodulator. A detector detects an amount of shift occurring in the PLL demodulator. A detector detects a gain of the amplifier. An FSK demodulator subjects a signal from the amplifier to FSK demodulation. An AFC unit detects a frequency offset in the signal from the amplifier and causes the signal generator to make a correction for the frequency offset detected.

A mixer is connected to a signal generator and an antenna and outputs a signal at an intermediate frequency. A PLL demodulator subjects the signal at the intermediate frequency from the mixer to PLL demodulation. An amplifier amplifies a signal from the PLL demodulator. A detector detects an amount of shift occurring in the PLL demodulator. A detector detects a gain of the amplifier. An FSK demodulator subjects a signal from the amplifier to FSK demodulation. An AFC unit detects a frequency offset in the signal from the amplifier and causes the signal generator to make a correction for the frequency offset detected.

An ultra-low power back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8 GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step down-conversion where the first mixing stage downconverts using the third harmonic of the local oscillator for power efficiency. The LP-65 nm CMOS receiver consumes 335 W with a sensitivity of 72 dBm at a BER of 10.sup.3 and data-rate of 31.25 kb/s. The radio uses a balun and a 250 kHz reference crystal as external components. The receiver uses a 1V supply voltage for analog blocks, and 0.85V for digital blocks including the local oscillator and the frequency-locked loop circuits.

A phase locked loop, for a particularly in a beamforming system comprises a loop filter (1) to provide a control signal (FC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback signal (FB) and a second feedback signal (FBD) in response to an oscillator signal (FO), the second feedback signal (FBD) delayed with respect to the first feedback signal (FB); a first comparator path (4) configured to receive the first feedback signal (FB) and a second comparator path (5) configured to receive the second feedback signal (FBD), each of the first and second comparator path (4, 5) configured to provide a respective current signal (CS1, CS2) to the loop filter (1) in response to a respective adjustment signal (FA1, FA2) and a phase deviation between a common reference signal (FR) and the respective feedback signal (FB, FBD).

A phase locked loop, for a particularly in a beamforming system comprises a loop filter (1) to provide a control signal (FC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback signal (FB) and a second feedback signal (FBD) in response to an oscillator signal (FO), the second feedback signal (FBD) delayed with respect to the first feedback signal (FB); a first comparator path (4) configured to receive the first feedback signal (FB) and a second comparator path (5) configured to receive the second feedback signal (FBD), each of the first and second comparator path (4, 5) configured to provide a respective current signal (CS1, CS2) to the loop filter (1) in response to a respective adjustment signal (FA1, FA2) and a phase deviation between a common reference signal (FR) and the respective feedback signal (FB, FBD).

A wireless communication device for asymmetrical frequency spreading including a processor configured to receive a frequency band message comprising a maximum difference and a minimum difference, wherein the maximum difference is between a maximum frequency of a sub-band and a signal frequency, and wherein the minimum difference is between the minimum frequency of the sub-band and the signal frequency compare the maximum difference and the minimum difference with each other; and generate a frequency shift based on the comparison.

A wireless communication device for asymmetrical frequency spreading including a processor configured to receive a frequency band message comprising a maximum difference and a minimum difference, wherein the maximum difference is between a maximum frequency of a sub-band and a signal frequency, and wherein the minimum difference is between the minimum frequency of the sub-band and the signal frequency compare the maximum difference and the minimum difference with each other; and generate a frequency shift based on the comparison.

The present technology relates to a signal processing apparatus and method which can suppress increase in power consumption. In an aspect of the present technology, control data, which is for controlling frequency modulation to a carrier signal using digital data to be transmitted, and for suppressing a time average of a fluctuation amount of a frequency modulation amount more than a case of controlling the frequency modulation to the carrier signal using the digital data is generated, the frequency modulation is performed to the carrier signal on the basis of the generated control data, and the carrier signal to which the frequency modulation is performed is transmitted as a transmission signal. The present technology can be applied to, for example, a signal processing apparatus, a transmission apparatus, a reception apparatus, a communication apparatus, or an electronic apparatus having a transmission function, a reception function, or a communication function, or a computer which controls these.

A locked loop circuit is disclosed. The locked loop circuit includes phase detection circuitry to generate a first error output based on a phase difference between a first reference input and a locked-loop output. Summing circuitry receives the first error output and a second error signal. The second error signal is based on one from a selection of error values. Oscillator/delay circuitry generates the locked-loop output. For a first mode of operation, the second error signal is based on a first selected error value. For a second mode of operation, the second error signal is based on a second selected error value different than the first selected error value.

A locked loop circuit is disclosed. The locked loop circuit includes phase detection circuitry to generate a first error output based on a phase difference between a first reference input and a locked-loop output. Summing circuitry receives the first error output and a second error signal. The second error signal is based on one from a selection of error values. Oscillator/delay circuitry generates the locked-loop output. For a first mode of operation, the second error signal is based on a first selected error value. For a second mode of operation, the second error signal is based on a second selected error value different than the first selected error value.