Apparatuses and methods related to digital mobile radio (DMR) with enhanced transceiver are disclosed herein. The transceiver detects waveforms of signals received by a digital mobile station radio (MS). By detecting whether the waveforms of the signals, the transceiver allows a digital baseband processor of the MS to remain in a sleep state while the signals are being detected by the DMR, thereby reducing an amount of power used while the signals are being detected.

A communication device includes a signal determiner determining whether there is a reception signal, and a period estimator estimating an interruption period of interruption of a signal transmitted from a device as a source of the reception signal, using a determination result from the signal determiner. The period estimator includes a differential operator calculating a differential value of the determination result, a masking operator calculating a provisional period of the interruption period using the differential value, controlling use of the differential value and provisional period based on internal state, and outputting the provisional period to be used, a period calculator calculating the interruption period using the provisional period, a signal existing section calculator calculating a signal existing section using the provisional period, a periodic timing estimator estimating periodic timing using the provisional period and signal existing section, and a state determiner determining the internal state using the interruption period.

A communication device includes a signal determiner determining whether there is a reception signal, and a period estimator estimating an interruption period of interruption of a signal transmitted from a device as a source of the reception signal, using a determination result from the signal determiner. The period estimator includes a differential operator calculating a differential value of the determination result, a masking operator calculating a provisional period of the interruption period using the differential value, controlling use of the differential value and provisional period based on internal state, and outputting the provisional period to be used, a period calculator calculating the interruption period using the provisional period, a signal existing section calculator calculating a signal existing section using the provisional period, a periodic timing estimator estimating periodic timing using the provisional period and signal existing section, and a state determiner determining the internal state using the interruption period.

A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.

Methods, systems and device for achieving synchronization in an orthogonal time frequency space (OTFS) signal receiver are described. An exemplary signal reception technique includes receiving an OTFS modulated wireless signal comprising pilot signal transmissions interspersed with data transmissions, calculating autocorrelation of the wireless signal using the wireless signal and a delayed version of the wireless signal that is delayed by a pre-determined delay, thereby generating an autocorrelation output, processing the autocorrelation filter through a moving average filter to produce a fine timing signal. Another exemplary signal reception technique includes receiving an OTFS modulated wireless signal comprising pilot signal transmissions interspersed with data transmissions, performing an initial automatic gain correction of the received OTFS wireless signal by peak detection and using clipping information, performing coarse automatic gain correction on results of a received and initial automatic gain control (AGC)-corrected signal.

Apparatuses and methods related to digital mobile radio (DMR) with enhanced transceiver are disclosed herein. The transceiver detects waveforms of signals received by a digital mobile station radio (MS). By detecting whether the waveforms of the signals, the transceiver allows a digital baseband processor of the MS to remain in a sleep state while the signals are being detected by the DMR, thereby reducing an amount of power used while the signals are being detected.

A signal demodulation apparatus and method for a closed communication system are provided. An analog voltage comparator is configured to convert a modulated signal and output the digital signal. The modulated signal is a 2ASK, 2FSK or 2PSK modulated signal. A sampling decider is configured to sample the digital signal to obtain a sampled digital signal. The sampling decider includes a high-frequency clock sampling circuit and a feature extracting and deciding circuit. The high-frequency clock sampling circuit is configured to sample the digital signal and to sample at least two points for a high level of any pulse of the digital signal. The feature extracting and deciding circuit is configured to extract a feature of the sampled digital signal to obtain an extracted feature of the sampled digital signal, and compare the extracted feature with features of known digital modulated signals to acquire a value represented by the digital signal.

A receiver for demodulating a pulse width modulated (PWM) signal, comprises: a voltage level shifter for shifting the PWM signal to predefined transistor voltage levels; a half-rate PWM decoder for receiving the shifted PWM signal; and a 2-bit-to-N-bit deserializer. The half-rate PWM decoder comprises a first decoder core, a second decoder core, a controller, and a sampler and retiming circuit. The first decoder core and the second decoder core are configured to decode alternating periods of the shifted PWM signal. The controller is coupled to the first decoder core, the second decoder core, the sampler and retiming circuit. The retiming circuit is configured to receive clock signals from the controller and to output half-rate even data from the first decoder core and half-rate odd data from the second decoder core. Outputs of the retiming circuit and an output of the controller are coupled to inputs of the deserializer.

A receiver for demodulating a pulse width modulated (PWM) signal, comprises: a voltage level shifter for shifting the PWM signal to predefined transistor voltage levels; a half-rate PWM decoder for receiving the shifted PWM signal; and a 2-bit-to-N-bit deserializer. The half-rate PWM decoder comprises a first decoder core, a second decoder core, a controller, and a sampler and retiming circuit. The first decoder core and the second decoder core are configured to decode alternating periods of the shifted PWM signal. The controller is coupled to the first decoder core, the second decoder core, the sampler and retiming circuit. The retiming circuit is configured to receive clock signals from the controller and to output half-rate even data from the first decoder core and half-rate odd data from the second decoder core. Outputs of the retiming circuit and an output of the controller are coupled to inputs of the deserializer.

A signal demodulation apparatus and method for a closed communication system are provided. An analog voltage comparator is configured to convert a modulated signal and output the digital signal. The modulated signal is a 2ASK, 2FSK or 2PSK modulated signal. A sampling decider is configured to sample the digital signal to obtain a sampled digital signal. The sampling decider includes a high-frequency clock sampling circuit and a feature extracting and deciding circuit. The high-frequency clock sampling circuit is configured to sample the digital signal and to sample at least two points for a high level of any pulse of the digital signal. The feature extracting and deciding circuit is configured to extract a feature of the sampled digital signal to obtain an extracted feature of the sampled digital signal, and compare the extracted feature with features of known digital modulated signals to acquire a value represented by the digital signal.