A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

A signal converter 100 includes, for at least two-phase signals detected by a resolver excited by a carrier signal having a carrier frequency fc, a first phase shifter 101 that shifts a phase of a first phase signal of the resolver with a pole at a frequency f1 lower than the carrier frequency fc, a second phase shifter 102 that shifts a phase of a second phase signal of the resolver with a pole at a frequency f2 higher than the carrier frequency fc, and a synthesizer 103 that combines the phase-shifted first phase signal with the phase-shifted second phase signal.

A signal detection method associated with a constellation diagram corresponding to a modulation scheme is provided for enhancing the reliability of code rate search. A mask is provided between two adjacent constellation points in the modulation scheme. The signal detection method includes: receiving a plurality of signals, and mapping the plurality of signals to the constellation diagram; when a first signal among the plurality of signals is located in the mask, discarding the first signal; and when a second signal among the plurality of signals outside located in the mask, determining a constellation point corresponding to the second signal.

A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.

Provided are a data modulation method and apparatus, a device, and a storage medium. The method includes: a modulation manner is configured, and data is modulated by using the modulation manner. That the constellation point modulation symbol of the modulation manner is formed by combining the first group of constellation point modulation symbols and the second group of constellation point modulation symbols includes: adjusting a phase of the second group of constellation point modulation symbols based on a phase of the first group of constellation point modulation symbols; and forming, based on a combination of the first group of and adjusted second group of constellation point modulation symbols, the constellation point modulation symbol of the modulation manner.

A signal converter 100 includes, for at least two-phase signals detected by a resolver excited by a carrier signal having a carrier frequency fc, a first phase shifter 101 that shifts a phase of a first phase signal of the resolver with a pole at a frequency f1 lower than the carrier frequency fc, a second phase shifter 102 that shifts a phase of a second phase signal of the resolver with a pole at a frequency f2 higher than the carrier frequency fc, and a synthesizer 103 that combines the phase-shifted first phase signal with the phase-shifted second phase signal.

A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

A signal converter 100 includes, for at least two-phase signals detected by a resolver excited by a carrier signal having a carrier frequency fc, a first phase shifter 101 that shifts a phase of a first phase signal of the resolver with a pole at a frequency f1 lower than the carrier frequency fc, a second phase shifter 102 that shifts a phase of a second phase signal of the resolver with a pole at a frequency f2 higher than the carrier frequency fc, and a synthesizer 103 that combines the phase-shifted first phase signal with the phase-shifted second phase signal.

A transmit power measurement apparatus includes a transmit power detection path, a compensation circuit and a tracking circuit. The compensation circuit includes a programmable filter device and a compensation controller. The programmable filter device generates a filter output. The compensation controller sets the programmable filter device at least based on a frequency response of the transmit power detection path. The tracking circuit generates a transmit power tracking result at least based on the filter output.

A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.