A method of dynamic range extension for heterodyne fiber-optic Interferometers, and more particularly towards the use of instantaneous carrier to extend the dynamic range of heterodyne fiber-optic interferometers. The method includes the providing of a heterodyne fiber-optic interferometer having a demodulator and an associated carrier frequency. The method also includes the determining of demodulator excessions. The detecting of the demodulator excessions and the determining of an appropriate correction factor is based on information from the instantaneous carrier frequency. The method also includes the introduction of the appropriate correction factor to the demodulator.

The present invention discloses BPSK demodulator, which uses a delay circuit to delay a BPSK signal and mixes the delayed BPSK signal with the undelayed BPSK signal to output a demodulated data signal, and which uses a phase rotation circuit and the demodulated data signal to obtain a carrier clock signal. The operating frequency of the delay circuit is the same as or 0.5 times the carrier frequency. Therefore, the present invention consumes less power and is realized by digital circuits and analog circuits.

A digital I/Q reprocessing demodulator and a process for significantly reducing arctangent computational loads. This is done by ensuring that all calculations are carried out in the linear part of the curve. The architecture of the demodulator is such that the demodulator 100 utilizes two I/Q stages. The first stage is utilized to determine a phase offset with regards to the free-running I/Q clocks. In the second processing stage, the phase of the I/Q reference signals are phase shifted based on the initial estimate such that the incoming carrier signal is nearly in-phase.

The present disclosure discloses a clock and data recovery circuit. A sampling circuit performs burst mode over-sampling on an input analog data signal according to a sampling timing in a burst mode to generate over-sampling results. A selection circuit determines neighboring two of the over-sampling results having opposite logic states in the burst mode to select data edge sampling results and data center sampling results interlaced with each other and having the same time period with input analog data signal from the over-sampling results accordingly to be output sampling results. A phase detection circuit performs phase detection according to the output sampling result to generate a phase locking direction. A phase adjusting circuit adjusts the sampling timing of the sampling circuit according to the phase locking direction to track the input analog data signal.

A demodulation device includes a phase rotation module, a phase adjustment module, a phase comparison module, and a reference signal generation module. The phase rotation module rotates phases of an I-Phase signal and a Q-Phase signal in a received signal of a multilevel PSK signal using a reference signal. The phase adjustment module adjusts the phases of the phase rotated I-Phase signal and the phase rotated Q-Phase signal output from the phase rotation module by multiplying the phases of the I-Phase signal and the Q-Phase signal with an integer value to generate a phase adjusted I-Phase signal and a phase adjusted Q-Phase signal. The phase comparison module compares the phase of the phase adjusted I-Phase signal with the phase of the phase adjusted Q-Phase signal to generate a phase comparison result. Also, the reference signal generation module generates a reference signal using the phase comparison result.

Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

A method and apparatus for performing residual phase noise compensation is described. A coarse carrier compensation of a received modulated signal is performed to obtain a coarse carrier compensated signal and a trellis-based residual carrier recovery is performed to estimate a residual phase noise of the coarse carrier compensated signal. The coarse carrier compensated signal is compensated based on the estimated residual phase noise.

Processing a digital bit stream and systems for implementing the methods are provided. The method includes dividing the digital bit stream into a plurality of data packets. In a first processing block performing a carrier recovery error calculation on a first portion of the plurality of data packets, comprising preforming a first phase locked loop (PLL) function on decimated data of the data packets and performing a carrier recovery operation on the first portion of the plurality of data packets. In a second processing block, in parallel with the processing of the first portion of the plurality of packets, performing the carrier recovery error calculation on a second portion of the plurality of data packets, comprising preforming the first PLL function on decimated data of the data packets and performing the carrier recovery operation on second portion of the plurality of data packets.