A demodulator for pulse-width modulated clock signals is disclosed. In one aspect, the demodulator includes an edge detector configured to detect transitions in a reference clock and output a signal indicative of timing of the detected transitions. The demodulator may also include a modulation detection circuit configured to identify modulation events of at least one pulse-width modulated pulse in the reference clock based on the signal output from the edge detector and output a signal indicative of the at least one pulse-width modulated pulse modulation event being identified. The demodulator may further include a retiming circuit configured to generate an output clock synchronized with the at least one pulse-width modulated pulse modulation event based on the signal output from the modulation detection circuit.

In some examples, a delay apparatus includes a controllable delay line comprising a plurality of delay elements selectively connected in a signal path to vary a delay of a signal passing through the delay line, and a controllable phase shifter comprising reflective loads adjustable to vary a phase shift applied to the signal.

A method of transmitting a Physical Layer Convergence Procedure (PLCP) frame in a Very High Throughput (VHT) Wireless Local Area Network (WLAN) system includes generating a MAC Protocol Data Unit (MPDU) to be transmitted to a destination station (STA), generating a PLCP Protocol Data Unit (PPDU) by adding a PLCP header, including an L-SIG field containing control information for a legacy STA and a VHT-SIG field containing control information for a VHT STA, to the MPDU, and transmitting the PPDU to the destination STA. A constellation applied to some of Orthogonal Frequency Division Multiplex (OFDM) symbols of the VHT-SIG field is obtained by rotating a constellation applied to an OFDM symbol of the L-SIG field.

System and method of timing recovery using calibration logic to correct non-idealities related to phase interpolation. The calibration logic includes a Look-Up Table (LUT) preloaded with a set of expected output phases of the interpolator. During operation, an input phase signal is quantized and supplied to the calibration logic. In response, the LUT outputs a subset of preloaded values that are closest to the quantized phase signal. Each preloaded value in the subset is compared with the input phase signal to identify the one that is closest to the input phase signal. The index of the identified preloaded value is used to correct the input phase signal. Thus, the input to the phase interpolator is calibrated based on a preloaded value that is closest to the input phase signal which is regarded as the desired phase shift to be achieved by the phase interpolator.

A wireless device detects a synchronization signal by obtaining (210), from a received signal, a sequence of samples, and calculating (220) a differentially decoded sequence from the obtained sequence of samples. The wireless device correlates (230) the calculated differentially decoded sequence with a first reference sequence corresponding to the synchronization signal, at each of a plurality of time offsets, and identifies which of the plurality of time offsets results in a largest correlation result. In response to determining (240) that the largest correlation result does not meet a predetermined reliability criterion, the wireless device correlates (250) the obtained sequence of samples with a second reference sequence, at each of a plurality of time and frequency offsets, and identifies which combination of time offset and frequency offset results in a largest correlation result. The first reference sequence comprises a differentially decoded version of the second reference sequence.

The present disclosure provides a demodulation method. The demodulation method includes obtaining a received signal; determining whether a multiuser interference is smaller than a threshold; performing a first signal detection operation on the received signal if the multiuser interference is smaller than the threshold, in which the first signal detection operation detects a single layer of spatial data in the received signal; and performing a second signal detection operation on the received signal if the multiuser interference is greater than the threshold, in which the second signal detection operation detects multiple layers of spatial data in the received signal.

Disclosed are embodiments of apparatuses and methods of use thereof for frequency domain (FD) chip level (CL) equalizers used in wireless receivers. The FD-CL-EQ may further selectively apply a higher order matrix inverse or a lower order matrix inverse in the calculation of a channel estimate based on whether interference is present or not. Further disclosed are embodiments of methods and apparatuses for estimating pilot signal-to-interference ratio (SIR) in the wireless receivers. Further disclosed are methods and apparatuses for compensating for phase errors in received demodulated data symbols to improve performance of the wireless receivers.

A likelihood generation apparatus for acquiring a likelihood of a 16QAM signal includes a first likelihood generation unit configured to generate a likelihood of each of two bits of a 16QAM signal point of the 16QAM signal from a relationship of each of an I-axis component and a Q-axis component with a likelihood when the 16QAM signal point is mapped on a constellation diagram, and a second likelihood generation unit configured to generate a likelihood of each of remaining two bits other than the two bits of the 16QAM signal point of the 16QAM signal based on a position of the 16QAM signal point in a lookup table, which is configured to input the I-axis component and the Q-axis component of the 16QAM signal point as arguments, and includes regions acquired by dividing the constellation diagram based on a possible value of each of the bits.

A BPSK demodulator circuit comprises: a sideband-separating and lower sideband signal-delaying unit which separates a modulated signal into a lower sideband and an upper sideband by a primary low pass filter and a primary high pass filter having a cut-off frequency as a carrier frequency, and which outputs an upper sideband analog signal and an analog signal delayed by of a cycle of the carrier frequency from a lower sideband analog signal; a data demodulating unit which demodulates digital data by means of latching, through a hysteresis circuit, an analog pulse signal appearing in accordance with the phase change part of a signal generated by the sum of the analog signals; and a data clock restoring unit which generates a data clock by using a data signal and a signal having the delayed lower sideband analog signal digitized through a comparator.

Disclosed are embodiments of apparatuses and methods of use thereof for frequency domain (FD) chip level (CL) equalizers used in wireless receivers. The FD-CL-EQ may further selectively apply a higher order matrix inverse or a lower order matrix inverse in the calculation of a channel estimate based on whether interference is present or not. Further disclosed are embodiments of methods and apparatuses for estimating pilot signal-to-interference ratio (SIR) in the wireless receivers. Further disclosed are methods and apparatuses for compensating for phase errors in received demodulated data symbols to improve performance of the wireless receivers.