Patent classifications
H04L27/2331
METHOD AND APPARATUS FOR TRANSMITTING PLCP FRAME IN WIRELESS LOCAL AREA NETWORK SYSTEM
A method of transmitting a Physical Layer Convergence Procedure (PLCP) frame in a Very High Throughput (VHT) Wireless Local Area Network (WLAN) system includes generating a MAC Protocol Data Unit (MPDU) to be transmitted to a destination station (STA), generating a PLCP Protocol Data Unit (PPDU) by adding a PLCP header, including an L-SIG field containing control information for a legacy STA and a VHT-SIG field containing control information for a VHT STA, to the MPDU, and transmitting the PPDU to the destination STA. A constellation applied to some of Orthogonal Frequency Division Multiplex (OFDM) symbols of the VHT-SIG field is obtained by rotating a constellation applied to an OFDM symbol of the L-SIG field.
METHODS AND APPARATUS FOR USING SYNCHRONIZATION SIGNALS AS REFERENCE FOR DEMODULATING MULTI-PORT BROADCAST CHANNEL
Various features related to using a multi-port synchronization signal as reference for demodulating a multi-port broadcast channel are described. In an aspect, a synchronization signal, e.g., SSS, may be repurposed to serve as a demodulation reference for a downlink channel, e.g., PBCH, thereby obviating the need for a base station to send an additional reference signal for PBCH demodulation. A base station may select two or more logical antenna ports to transmit a synchronization signal, transmit the synchronization signal from the selected two or more logical antenna ports, and transmit information on the PBCH, from at least the selected two or more logical antenna ports. A UE may receive the synchronization signal from the two or more logical antenna ports at the base station, receive information on the PBCH from the at least the two or more logical antenna ports, and demodulate the information based on the received synchronization signal.
Systems and methods for frequency synchronization between transmitters and receivers in a communication system
Systems and methods which provide training sequence or preamble-based synchronization with respect to non-coherent modulated signals and/or differentially coherent modulated signals are described. Embodiments provide for time synchronization using a technique for mitigating the effect of carrier frequency offset (CFO) with respect to the received signal. Embodiments of the present invention provide for frequency synchronization using a technique for estimating CFO using a constant bias induced with respect to the received signal by CFO. Additionally or alternatively, embodiments of the present invention provide for frequency synchronization using a technique for estimating CFO using phase rotation caused by CFO. The time synchronization and frequency synchronization of embodiments may be performed independently, without requiring the results of one synchronization operation for performing the other synchronization operation.
Method and apparatus for transmitting PLCP frame in wireless local area network system
A method of transmitting a Physical Layer Convergence Procedure (PLCP) frame in a Very High Throughput (VHT) Wireless Local Area Network (WLAN) system includes generating a MAC Protocol Data Unit (MPDU) to be transmitted to a destination station (STA), generating a PLCP Protocol Data Unit (PPDU) by adding a PLCP header, including an L-SIG field containing control information for a legacy STA and a VHT-SIG field containing control information for a VHT STA, to the MPDU, and transmitting the PPDU to the destination STA. A constellation applied to some of Orthogonal Frequency Division Multiplex (OFDM) symbols of the VHT-SIG field is obtained by rotating a constellation applied to an OFDM symbol of the L-SIG field.
Ultra low power wideband non-coherent binary phase shift keying demodulator using first order sideband filters with phase zero alignment
An embodiment of the present invention relates to an ultra low power wideband asynchronous binary phase shift keying (BPSK) demodulation method and a circuit configuration thereof. The ultra low power wideband asynchronous BPSK demodulation circuit comprises a sideband division and upper sideband signal delay unit dividing a modulated signal into an upper sideband and a lower sideband by a first order high-pass filter and a first order low-pass filter; a data demodulation unit latching, through a hysteresis circuit, a signal generated by a difference between the analog signals in which a phase difference between the delayed upper sideband analog signal and the lower sideband analog signal is aligned at 0, so as to demodulate digital data; and a data clock recovery unit for generating a data clock by using a signal digitalized from the lower sideband analog signal through a comparator and a data signal.
QPSK demodulator
A novel quadrature phase-shift keying (QPSK) demodulator, called the bowknot quadrature phase-shift keying (BQPSK) demodulator, is disclosed. The BQPSK demodulator uses a delay circuit to delay a BQPSK signal and mixes the delayed BQPSK signal with the undelayed BQPSK signal to output an I-channel data signal and a Q-channel data signal. The BQPSK demodulator further uses a phase rotation circuit to demodulate the orthogonal data signals and obtain a recovery clock signal. The BQPSK demodulator neither uses an A/D converter nor uses a quadrature oscillator, featuring high data rate, low power consumption, simple architecture and superior reliability. The BQPSK demodulator can be realized by digital circuits and analog circuits.
Methods and apparatuses for advanced receiver design
Disclosed are embodiments of apparatuses and methods of use thereof for frequency domain (FD) chip level (CL) equalizers used in wireless receivers. The FD-CL-EQ may further selectively apply a higher order matrix inverse or a lower order matrix inverse in the calculation of a channel estimate based on whether interference is present or not. Further disclosed are embodiments of methods and apparatuses for estimating pilot signal-to-interference ratio (SIR) in the wireless receivers. Further disclosed are methods and apparatuses for compensating for phase errors in received demodulated data symbols to improve performance of the wireless receivers.
METHODS AND APPARATUSES FOR ADVANCED RECEIVER DESIGN
Disclosed are embodiments of apparatuses and methods of use thereof for frequency domain (FD) chip level (CL) equalizers used in wireless receivers. The FD-CL-EQ may further selectively apply a higher order matrix inverse or a lower order matrix inverse in the calculation of a channel estimate based on whether interference is present or not. Further disclosed are embodiments of methods and apparatuses for estimating pilot signal-to-interference ratio (SIR) in the wireless receivers. Further disclosed are methods and apparatuses for compensating for phase errors in received demodulated data symbols to improve performance of the wireless receivers.
SYSTEMS AND METHODS FOR FREQUENCY SYNCHRONIZATION BETWEEN TRANSMITTERS AND RECEIVERS IN A COMMUNICATION SYSTEM
Systems and methods which provide training sequence or preamble-based synchronization with respect to non-coherent modulated signals and/or differentially coherent modulated signals are described. Embodiments provide for time synchronization using a technique for mitigating the effect of carrier frequency offset (CFO) with respect to the received signal. Embodiments of the present invention provide for frequency synchronization using a technique for estimating CFO using a constant bias induced with respect to the received signal by CFO. Additionally or alternatively, embodiments of the present invention provide for frequency synchronization using a technique for estimating CFO using phase rotation caused by CFO. The time synchronization and frequency synchronization of embodiments may be performed independently, without requiring the results of one synchronization operation for performing the other synchronization operation.
Methods and apparatuses for advanced receiver design
Disclosed are embodiments of apparatuses and methods of use thereof for frequency domain (FD) chip level (CL) equalizers used in wireless receivers. The FD-CL-EQ may further selectively apply a higher order matrix inverse or a lower order matrix inverse in the calculation of a channel estimate based on whether interference is present or not. Further disclosed are embodiments of methods and apparatuses for estimating pilot signal-to-interference ratio (SIR) in the wireless receivers. Further disclosed are methods and apparatuses for compensating for phase errors in received demodulated data symbols to improve performance of the wireless receivers.