A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.

A hardware module comprises at least a first ingress buffer and a second ingress buffer, where the second ingress buffer holds data packets from a plurality of source components. To ensure fairness between one or more sources providing data to the first ingress buffer and the plurality of sources providing data to the second ingress buffer, processing circuitry examines source identifiers in packets held in the second ingress buffer and selects between the buffers so as to arbitrate between the sources. In some embodiments, the examination of the source identifiers provides statistics for a weighted round robin between the ingress buffers. In other embodiments, the source identifier of whichever packet is currently at the head of the second ingress buffer is used to perform a simple round robin between the sources.

A data processing apparatus (1) includes a signal processing unit (31, 32) and an insertion/deletion unit (33). The signal processing unit performs predetermined signal processing on the wirelessly received data for each frame that includes a predetermined number of samples, and stores the data in the buffers (41, 42). In the case where an amount of the data accumulated in the buffer is out of a predetermined range, the insertion/deletion unit (33) performs insertion/deletion processing that inserts or deletes the data in units of samples.

A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.

A packet control method, a flow table update method, and a node device including a first queue and a second queue, where the method includes: obtaining, by the node device, a first packet; determining, by the node device, that a data flow to which the first packet belongs is marked as an isolated flow; and if the first queue and/or the second queue meet and/or meets a first preset condition, controlling, by the node device, the first packet to enter the first queue and wait to be scheduled; or if the first queue and/or the second queue meet and/or meets a second preset condition, controlling, by the node device, the first packet to enter the second queue and wait to be scheduled.

Techniques for providing request throttling using proportional, integral, and exponential smoothing algorithms are disclosed. A distributed computing system can include a throttler engine that receives a plurality of requests targeting a software component within the distributed computing system. The throttler engine can aggregate the requests into a queue based on a time window. The throttler engine can determine a received request rate and a request rate limit for the software component and then compute a throttled request rate. The throttled request rate can include correction terms derived from proportional and integral computations and a correction term obtained from an exponential smoothing algorithm. The throttler engine can then provide throttled requests from the queue to the software component.

In a switching system that comprises a central switching device an at least one port extender device, the central switching device includes at least one port configured to interface with the port extender device, and the port extender device includes a plurality of front ports for interfacing with one or more networks. The central switching device includes a processor that processes packets received from the at least one port extender device, and a plurality of egress queues for storing processed packets that are to be forwarded to the at least one port extender device for transmission via ones of the front ports. The central switching device also includes a flow control processor configured to, responsively to flow control messages received from the at least one port extender device, control transmission of packets to the at least one port extender device to prevent overflow of egress queues of the port extender device.

Methods and systems are provided for performing lossy dropping and ECN marking in a flow-based network. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow are acknowledged after reaching the egress point of the network, and the acknowledgement packets are sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and perform per-flow packet dropping and ECN marking.

Some embodiments provide a network forwarding integrated circuit (IC) that includes at least one packet processing pipeline. The packet processing pipeline includes multiple match-action stages, at least one of which includes a stateful processing unit that operates at a line rate of the network forwarding IC. The stateful processing unit is configured to receive data stored in a memory location associated with a stateful table of the match-action stage. The data includes a set of values. The stateful processing unit is further configured to identify one of a maximum value and a minimum value from the set of values, and to output the identified value for use by a next match-action stage.

Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.