Examples described herein relate to a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine a path to transmit a packet based on relative network traffic transmitted via multiple paths. In some examples, determine a path to transmit a packet is based on Deficit Round Robin (DRR). In some examples, the programmable packet processing pipeline circuitry includes: a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes, a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and at least one child node is associated with the determined path.

Examples described herein relate to a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine a path to transmit a packet based on relative network traffic transmitted via multiple paths. In some examples, determine a path to transmit a packet is based on Deficit Round Robin (DRR). In some examples, the programmable packet processing pipeline circuitry includes: a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes, a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and at least one child node is associated with the determined path.

The disclosed systems and methods provide hyperscalar packet processing. A method includes receiving a plurality of network packets from a plurality of data paths. The method also includes arbitrating, based at least in part on an arbitration policy, the plurality of network packets to a plurality of packet processing blocks comprising one or more full processing blocks and one or more limited processing blocks. The method also includes processing, in parallel, the plurality of network packets via the plurality of packet processing blocks, wherein each of the one or more full processing blocks processes a first quantity of network packets during a clock cycle, and wherein each of the one or more limited processing blocks processes a second quantity of network packets during the clock cycle that is greater than the first quantity of network packets. The method also includes sending the processed network packets through data buses.

In one embodiment, a system comprising a network interface controller comprising circuitry to determine per-flow analytics information for a plurality of packet flows; and facilitate differential rate processing of a plurality of packet queues for the plurality of packet flows based on the per-flow analytics information.

A method for data transmission may be implemented on an electronic device having one or more processors. The one or more processors may include a master queue including a master queue head and a plurality of primary ports that are connected to each other using a serial link. The method may include operating the master queue head to obtain a message. The method may also include operating the master queue head to segment the message into a plurality of segments. The method may also include operating the master queue head to transmit the plurality of segments to a first primary port of the plurality of primary ports in the master queue. The method may also include operating the first primary port to transmit the plurality of segments to a second primary port of the plurality of primary ports in the master queue.

An information processing apparatus includes a processor that obtains a flow table from a switch apparatus that processes packets by using the flow table. The processor creates, for each flow registered with the flow table, a verification packet based on identification information that identifies each flow. The processor determines a number of verification packets based on a count value that represents a number of actual packets that have arrived at the switch apparatus. The processor generates the number of verification packets for each flow by copying the verification packet created for each flow. The processor determines transmission order of the generated verification packets based on the count value for each flow and time information that represents a time when a final actual packet of each flow has arrived at the switch apparatus.

An embodiment provides a method for transferring information utilizing a serial communication command structure over an unreliable or a non-continuous communication channel, including: establishing a serial command structure, wherein the establishing comprises defining a package structure having a predefined format, wherein the serial command structure comprises bounded data; and transmitting, over the unreliable or the non-continuous communication channel, data from a sending entity to a receiving entity utilizing the serial command structure and in the predefined format. Other aspects are described and claimed.

A load distribution system has: determination means for determining, upon an input port receiving a packet, a flow attribute indicating whether a flow configured by the packet is a flow that tends to include many long packets or a flow that tends to include many short packets; and output means for outputting the packet to a packet transfer device in a load state indicating that a load applied by the flow of the flow attribute is low, of a plurality of packet transfer devices, in accordance with the flow attribute determined by the determination means.

The disclosed systems and methods provide hyperscalar packet processing. A method includes receiving a plurality of network packets from a plurality of data paths. The method also includes arbitrating, based at least in part on an arbitration policy, the plurality of network packets to a plurality of packet processing blocks comprising one or more full processing blocks and one or more limited processing blocks. The method also includes processing, in parallel, the plurality of network packets via the plurality of packet processing blocks, wherein each of the one or more full processing blocks processes a first quantity of network packets during a clock cycle, and wherein each of the one or more limited processing blocks processes a second quantity of network packets during the clock cycle that is greater than the first quantity of network packets. The method also includes sending the processed network packets through data buses.

Methods, systems, and apparatuses for discovering dynamic path maximum transmission unit (PMTU) between a sending computing device and a receiving computing device (e.g., a client device and a host device) are described herein. A sending computing device may iteratively transmit bursts of probe packets, each burst being defined by a search range between a maximum packet size and a minimum packet size. The sending computing device may iteratively update the search range based on the previous iteration until the search converges on the PMTU. When the PMTU is discovered, each of the computing devices may update their transport and presentation layer buffers based on the discovered PMTU without any other protocol level disruption. In a multi-path scenario, the computing device may discover PMTU for each of the paths and select a performance optimal path based on the individual PMTUs and other network characteristics such as loss, latency, and throughput.