Provided are a stereoscopic distance measuring apparatus and method, and a computer readable program. The apparatus includes first and second optical cameras, first and second position-posture meters, an image corrector, and a stereoscopic distance measuring unit. The first and second position-posture meters acquire first and second position-posture information regarding the first and second optical cameras. The image corrector corrects, on the basis of the first and second position-posture information, positions and orientations of a plurality of first and second images taken by the first and second optical cameras, to generate a plurality of first and second corrected images. The stereoscopic distance measuring unit calculates a distance to a photographing target, on the basis of a pair of the corrected images including one of the plurality of the first corrected images and one of the plurality of the second corrected images.

A stereo distance measuring apparatus includes a first optical camera and a second optical camera, a position-posture calculator, an image corrector, and a stereo distance measuring unit. The first and second optical cameras are provided in an elastic structure part of an aircraft and separated from each other. The first and second optical cameras constitute a stereo camera. The position-posture calculator calculates, on the basis of a displacement amount of the elastic structure part, first and second position-posture information regarding positions and postures of the first and second optical cameras, respectively. The image corrector generates first and second corrected images by correcting, on the basis of the first and second position-posture information, positions and orientations of images taken by the first and second optical cameras, respectively. The stereo distance measuring unit calculates a distance to a photographing target, on the basis of the first and second corrected images.

A camera module includes a lens barrel holder and a substrate. The substrate may include a circuit board embedded in the substrate. The circuit board may include multiple electrical components mounted to a first side of the circuit board, where the electrical components are not exposed outside. The circuit board may also include multiple electrical connections on another side of the circuit board, an image sensor mounted to the electrical connections, and an upper opening in the circuit board for light to pass through. The substrate may include an upper opening configured to receive, at least partially inside the substrate, a lower portion of the lens barrel holder. The substrate may include a lower opening connected to the upper opening and configured to receive the image sensor. The lens barrel holder may include extensions, such as a flange or tabs, and an adhesive bond between the extensions and the substrate.

A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region and a logic region. A first resist protect oxide (RPO) is formed over the pixel region, but not over the logic region. Silicide contacts are formed on the top of active devices formed in the pixel region, but not on the surface of the substrate in the pixel region, and silicide contacts are formed both on the top of active devices and on the surface of the substrate in the logic region. A second RPO is formed over the pixel region and the logic region, and a contact etch stop layer is formed over the second RPO. These layers help to reflect light back to the image sensor when light impinges the sensor from the backside of the substrate, and also helps prevent damage that occurs from overetching.

A solid-state imaging device including: a pixel array unit in which a plurality of pixels outputting an analog pixel signal are arranged in a two-dimensional matrix form; a ramp signal generation unit configured to generate and output a ramp wave; a clock generation unit configured to generate and output multiphase clocks; and a signal-processing unit, wherein the signal-processing unit including: a plurality of analog-to-digital conversion circuits, and a plurality of repeater circuits, wherein each of the plurality of analog-to-digital conversion circuits includes: a comparison unit, and a latch unit, wherein each of the plurality of the analog-to-digital conversion circuits outputs the digital value according to the state of the phase held by each latch circuit, and wherein each of the plurality of the repeater circuits corresponding to the same set are arranged side by side, and the repeater circuits are connected in series.

In a solid-state image sensing apparatus of an addressing method, a clock-conversion part generates a high-speed clock signal having a frequency two times or more the frequency of a low-speed clock signal. A signal processing part receives 10-bit pixel data through a horizontal signal line, performs predetermined signal processing, and passes parallel-format data to a switching part. The switching part selects each one bit of the parallel-format 10-bit data in a predetermined sequence to output from an output terminal using the high-speed clock signal from the clock-conversion part as a switching command, thus converts the parallel-format data into serial-format data, and passes it to an output buffer. The output buffer externally outputs differential output of normal video data and inverted video data individually from output terminals. Accordingly, the problems in power consumption, noises, and unnecessary radiation are solved, and higher-speed output is achieved.

Disclosed herein is a circuit comprising a first thin film transistor (TFT) and storage capacitor having a first electrode and a second electrode configured to face to each other. A second TFT is coupled to the capacitor, wherein a first gate electrode of the first TFT, a first electrode of the storage capacitor and a second gate electrode of the second TFT are integrally formed.

The invention discloses a pixel acquisition circuit, an optical flow sensor, and an image acquisition system. Therein, the optical flow sensor comprises a pixel acquisition circuit array, a waveform generator, a global control unit, and a readout unit. The pixel acquisition circuit array comprises the pixel acquisition circuits in accordance with the invention. The waveform generator is operative to output a periodic signal waveform to the time signal line coupled with each of the pixel acquisition circuits in the array. The global control unit is operative to output said global activation signal to each pixel acquisition circuit through the global trigger signal line, and output a reset signal to each pixel acquisition circuit through said reset signal line. The readout unit is operative to read the signals output by at least a part of the pixel acquisition circuits in that array.

A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell includes two pixels. Upper and lower photoelectric converters and, transfer transistors and connected to the upper and lower photoelectric converters, respectively, a reset transistor, and an amplifying transistor form the two pixels. A full-face signal line is connected to the respective drains of the reset transistor and the amplifying transistor. Controlling the full-face signal line, along with transfer signal lines and a reset signal line, to read out signals realizes the simplification of the wiring in the pixel, the reduction of the pixel size, and so on.

Disclosed herein is a photo sensor comprising a first thin film transistor (TFT) configured to convert light energy to electric energy; a storage capacitor having a first electrode and a second electrode configured to face to each other, and storing the electric energy from the first TFT as charge; and a second TFT configured to output the charge stored in the storage capacitor according to a control signal, wherein a first gate electrode of the first TFT, a first electrode of the storage capacitor and a second gate electrode of the second TFT are integrally formed.