An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

Methods and systems for managing content items are described. A content item may be separated into components, such as chroma components, luminance components, and audio components. For more efficient management of the content, including for storage and delivery of the content, the separate components may be stored at different locations. For example, chroma components may be stored on a central server, while luminance and audio components are stored at other locations, such as edge servers, or vice versa, to accommodate network efficiency considerations. When content is delivered to a player, two or more separate streams carrying different content components may be delivered to the player.

Methods and systems for managing content items are described. A content item may be separated into components, such as chroma components, luminance components, and audio components. For more efficient management of the content, including for storage and delivery of the content, the separate components may be stored at different locations. For example, chroma components may be stored on a central server, while luminance and audio components are stored at other locations, such as edge servers, or vice versa, to accommodate network efficiency considerations. When content is delivered to a player, two or more separate streams carrying different content components may be delivered to the player.

An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

Disclosed is a video processor for a magnifier camera. In particular, the disclosure relates to a video processor that eliminates the use of a frame buffer. This, in turn, reduces the latency otherwise present in the video signal. The disclosed video processor also allows selected portions of the display to be shaded. This highlights the non-shaded portions of the display while at the same time allowing the entire object to be perceived by the user.

Disclosed is a video processor for a magnifier camera. In particular, the disclosure relates to a video processor that eliminates the use of a frame buffer. This, in turn, reduces the latency otherwise present in the video signal. The disclosed video processor also allows selected portions of the display to be shaded. This highlights the non-shaded portions of the display while at the same time allowing the entire object to be perceived by the user.

An apparatus and method for intra-predicting an image are provided. The method includes: obtaining, based on restored neighboring pixels of a chrominance block and restored neighboring pixels of a luminance pixel corresponding to the chrominance block, parameters representing a correlation between the chrominance block that is to be intra-predicted and a luminance block; and predicting, using the parameters, the chrominance block from the luminance block, wherein the obtaining the parameters includes performing a predetermined operation on the restored neighboring pixels of the chrominance block and the restored neighboring pixels of the luminance block, and wherein the predetermined operation comprises an adaptive scaling process of changing bit depths of the parameters to reduce a size of a look-up table and prevent an occurrence of overflow.