Patent classifications
H04N21/42692
Automatically or semi-automatically transferring configuration information in connection with a media device upgrade
A facility for transferring configuration information to a target media device is described. The facility receives in the target media device a copy of media device settings stored in a source media device distinct from the target media device in a first form in which they are used in the source media device. This copy of media device settings is received by the target media device via a route other than its visual user interface. The facility causes the received copy of media device settings to be transformed into a second form in which they can be used in the target media device. The facility then stores the media receiver settings in the second form in the target media device for use by the target media device.
DYNAMIC LOAD BALANCING FOR VIDEO ANALYTICS PIPELINES
In one embodiment, an edge compute node comprises processing circuitry to: receive an incoming video stream captured by a camera, wherein the incoming video stream comprises a plurality of video segments; store the plurality of video segments in a receive buffer in a memory; perform a visual computing task on a first video segment in the receive buffer; detect a resource overload on the edge compute node; receive load information corresponding to a plurality of peer compute nodes; select a peer compute node to perform the visual computing task on a second video segment in the receive buffer; replicate the second video segment from the edge compute node to the peer compute node; and receive a compute result from the peer compute node, wherein the compute result is based on the peer compute node performing the visual computing task on the second video segment.
DATA PROCESSING METHOD AND RELATED PRODUCT
Provided is a data processing system. The system includes a data source, a data receiver, a plurality of source code data frame buffer regions, a data processing module and a state register. The data source is configured to generate a data frame, the data receiver is configured to receive the data frame, and write the data frame into one of a plurality of data frame buffer regions, each of the plurality of source code data frame buffer regions is configured to store a data frame to be processed, the data processing module is configured to perform subsequent processing on data and the state register is configured to store a state of the system and states of the plurality of source code data frame buffer regions.
MACRO AND SRAM BIT CELL COOPTIMIZATOIN FOR PERFORMANCE (LONG/SHORTWORDLINE COMBO SRAM)
A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.
SOLID-STATE IMAGING ELEMENT AND ELECTRONIC DEVICE
An imaging device and an electronic apparatus including an imaging device are provided. The imaging device includes a substrate and a photoelectric conversion film disposed above the substrate. A first pixel includes a first photoelectric conversion film region, first and second photoelectric conversion regions formed in the substrate, and a vertical transistor for the first photoelectric conversion element. A second pixel includes a second photoelectric conversion film region, first and second photoelectric conversion regions formed in the substrate, and a vertical transistor for the first photoelectric conversion element. The imaging device also includes a first floating diffusion. The first floating diffusion is shared by the first photoelectric conversion regions of the first and second pixels. A portion of the first photoelectric conversion regions of the respective pixels is between a light incident surface of the substrate and the vertical transistor for the respective pixel.
Solid-state imaging element and electronic device
An imaging device and an electronic apparatus including an imaging device are provided. The imaging device includes a substrate and plurality of pixel regions, wherein each pixel region includes: a first photoelectric conversion portion that performs photoelectric conversion according to a first wavelength of incident light; a first reading portion that reads charges converted by the first photoelectric conversion portion; a first storage unit that is formed between adjacent pixels and stores the charges read by the first reading portion; a second photoelectric conversion portion that performs photoelectric conversion according to a second wavelength different from the first wavelength; a second reading portion that reads charges converted by the second photoelectric conversion portion; and a second storage unit that is formed between adjacent pixels and stores the charges read by the second reading portion.
Dynamic load balancing for video analytics pipelines
In one embodiment, an edge compute node comprises processing circuitry to: receive an incoming video stream captured by a camera, wherein the incoming video stream comprises a plurality of video segments; store the plurality of video segments in a receive buffer in a memory; perform a visual computing task on a first video segment in the receive buffer; detect a resource overload on the edge compute node; receive load information corresponding to a plurality of peer compute nodes; select a peer compute node to perform the visual computing task on a second video segment in the receive buffer; replicate the second video segment from the edge compute node to the peer compute node; and receive a compute result from the peer compute node, wherein the compute result is based on the peer compute node performing the visual computing task on the second video segment.
Optimized static random access memory
A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.
AUTOMATICALLY OR SEMI-AUTOMATICALLY TRANSFERRING CONFIGURATION INFORMATION IN CONNECTION WITH A MEDIA DEVICE UPGRADE
A facility for transferring configuration information to a target media device is described. The facility receives in the target media device a copy of media device settings stored in a source media device distinct from the target media device in a first form in which they are used in the source media device. This copy of media device settings is received by the target media device via a route other than its visual user interface. The facility causes the received copy of media device settings to be transformed into a second form in which they can be used in the target media device. The facility then stores the media receiver settings in the second form in the target media device for use by the target media device.
Storage System and Method for Time-Based Data Retrieval
A storage system and method for time-based data retrieval are provided. In one embodiment, a controller of the storage system is configured to receive time information from a host; receive a write command from the host, wherein the write command comprises a logical block address; and create a time-to-logical-block-address map from the time information and the logical block address received from the host. Other embodiments are provided.