Systems, methods, and devices implement video streaming. Methods include receiving video data from a video source, the video data comprising at least one video frame, and determining a plurality of store parameters associated with a store operation and a plurality of fetch parameters associated with a fetch operation for a portion of the video data, wherein the plurality of store parameters and the plurality of fetch parameters identify whether a fetch unit or a store unit should be stalled. Methods also include implementing a store operation in a buffer for a designated number of lines of the video data based on the plurality of store parameters. Methods additionally include implementing a fetch operation from the buffer for the designated number of lines of the video data based on the plurality of fetch parameters.

Audio and video devices can be virtualized using synchronous A/V streaming. When a video device such as a webcam is connected to a client terminal while the client terminal has established a remote session on a server, video data generated by the video device can be encoded into an encoded video stream using the H.264 or similar standard. Additionally, audio data corresponding to the video data can be embedded into the encoded video stream. The encoded video stream with the embedded audio can then be transferred to the server. The server-side components can extract the audio from the stream and perform the necessary decoding on the video and possibly on the audio data prior to providing the decoded data to drivers that function as virtualized audio and video devices on the server.

Described herein are systems and methods for providing hardware based security to software applications in a television receiver. The system can include a television receiver having a trusted hardware environment that includes a security processor and a standard environment that includes an application processor. The security processor can ensure that at least a portion of the software application executed by the application processor is secure. A portion of the software application code can be placed in an interrupt service routine memory space. During execution of the software application, the security processor can security check the portion of the software application in the interrupt service routine memory space, making it trusted code. The security processor can force the application processor to execute the trusted code by triggering an interrupt. Such forced execution can allow the security processor to not only ensure that code is trusted, but that it is executed.

A semiconductor device that is suitable for high-speed operation is provided. The semiconductor device includes a decoder. The decoder includes a first circuit. The first circuit is configured to operate in synchronization with a clock signal. The first circuit is configured to perform image processing. A circuit configuration of the first circuit can be changed. Clock gating is performed on the first circuit to prevent the clock signal from being input to the first circuit when the circuit configuration of the first circuit is being changed. A broadcasting system including the semiconductor device is also provided.

A de-interleaving circuit that performs a time de-interleaving process on an interleaved block of an interleave signal includes: an input buffer, buffering multiple information units included in a time interleaved block; a writing address generator, generating multiple writing addresses according to a predetermined rule to write the information units buffered in the input buffer to a memory; a reading address generator, generating multiple reading addresses according to the predetermined rule to read the information units from the memory; and an output buffer, buffering the information units read from the memory. The information units are stored in multiple tiles of the memory. The tiles correspond to multiple regions of the time interleaved block, the multiple regions include a first region and a second region, and the dimensions of each tile in the first region are different from the dimensions of each tile in the second region.

A vehicle event recorder is provided that includes a camera for capturing a video as discrete image frames, and that further includes a managed loop memory and a management system for generating a virtual timeline dilation effect. To overcome size limits in the buffer memory of the video event recorder, the maximum time extension of a video series is increased by enabling a reduction in temporal resolution in exchange for an increase in the temporal extension. Memory cells are overwritten in an interleaved fashion to produce a reduced frame rate for the recording of certain time periods connected to an event moment. In time periods furthest from the event moment, the resulting frame rate is minimized while in time periods closest to the event moment, the resulting frame rate is maximized.

Methods and systems for processing video data are disclosed herein and may comprise receiving within a single mobile multimedia processor chip integrated within a mobile device, a secure key from an off-chip device integrated within the mobile device. The secure key may be decrypted within the single mobile multimedia processor chip, utilizing an on-chip key. The decrypted secure key may be stored within the single mobile multimedia processor chip. The received encrypted data may be decrypted within the single mobile multimedia processor chip, using the stored, decrypted secure key. The on-chip key may be stored within a one-time programmable (OTP) memory in the single mobile multimedia processor chip. The stored on-chip key may be retrieved from the OTP memory for the decrypting. The stored decrypted received secure key may be encrypted utilizing the on-chip key stored within the single mobile multimedia processor chip.

A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.

A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.