In an FPGA device, an FPGA receiver is configured to receive a serial signal, to deserialize the received serial signal into a parallel signal, and to align parallel words in the parallel signal. Programmable FPGA fabric in the FPGA device is coupled to receive the parallel signal from the FPGA receiver. The programmable FPGA fabric is also configured to descramble data words from the parallel words in the parallel signal, to perform a phase detection operation based on the descrambled data words, to generate an alignment control signal based on the phase detection operation, and to feed back the alignment control signal to the FPGA receiver to control alignment of the parallel words in the parallel signal. The serial signal is a Serial Digital Interface (SDI) signal in an embodiment.

A transmission/reception system 1 includes a transmission device 10 configured to transmit image data and a reception device 20 configured to receive the image data transmitted from the transmission device 10. The transmission device 10 includes a serializer 11, an encoding unit 12, a data buffering unit 13, a data selection unit 14, a counter 15, and a synchronization signal generation unit 16. The data buffering unit 13 buffers data every n bits in synchronization with the clock. The data selection unit 14 outputs m-bit data selected from the data buffered by the data buffering unit 13 on the basis of a count value from the counter 15.

The present technology relates to a signal processing apparatus, a signal processing method, a program, and a signal transmission system realizing an SDI (serial digital interface) capable of effectively transmitting an audio stream together with video data, for example, of which the frame rate is 100 Hz or 120 Hz. An audio multiplexing unit multiplexes an audio sample into a data area of horizontal lines of n2 (here, 2n2n1) rows after a first horizontal line in which the audio sample is generated, which is a predetermined data area arranged within a horizontal blanking area disposed for each horizontal line of video data in a data stream defined in a format of an SDI used for transmitting the video data, in a case where an audio is sampled at an interval of once or less for horizontal lines of n1 (here, n12) rows of the video data of a predetermined frame rate. For example, the present technology can be applied to a broadcast camera.

A video processing device for virtual reality is provided. The video processing device includes a video input mechanism configured to receive a first and a second original video obtained from a first camera device; a video processing mechanism in transmission connecting to the video input mechanism, the video processing mechanism includes a first video processing unit configured to adjust the first and the second original video to a first video and a second video, the first video processing unit is configured to further combine the first video and the second video into a third video having a 16:9 aspect ratio, and dimensions of the third video being a total of those of the first and the second video; and a video output mechanism in transmission connecting to the video processing mechanism through a physical wire. A video generating system for virtual reality is also provided.

A video multiviewer system may include a plurality of video scalers operating in parallel for generating initially scaled video streams by performing video scaling in at least one dimension on a plurality of video input streams. The video multiviewer system may also include a processing unit coupled downstream from the video scalers for generating additionally scaled video streams by performing additional video scaling on the initially scaled video streams, and a display cooperating with the processing unit for displaying multiple video windows based upon the additionally scaled video streams.

Provided herein is a controlling method of a broadcast receiving apparatus, the controlling method including receiving a Transport Stream (TS) packet from an external source; extracting a Program Clock Reference (PCR) and a time stamp from the TS packet; computing a difference value between the PCR value and the time stamp value; generating a system timing clock based on the computed difference value and a buffering time during which the broadcast receiving apparatus decodes an Elementary Stream (ES) packet included in the TS packet; and decoding the ES packet based on the generated system timing clock.

Embodiments of the present disclosures provide a method, system and apparatus for transmitting intelligent information. When one frame of video data x is to be transmitted, a SDI sending terminal determines whether there is intelligent information satisfying a transmission condition; the transmission condition comprising that intelligent information is not transmitted and transmission of a frame of video data corresponding to the intelligent information is finished. If there is the intelligent information satisfying the transmission condition, the SDI sending terminal adds intelligent information y being one item of the intelligent information satisfying the transmission condition into a preset position of the video data x; and transmits the video data x having the intelligent information y. By using the solutions of the present disclosures, implementation costs are reduced and security is improved.

The invention provides a method for mapping a data stream onto an SDI channel, said data stream comprising a sequence of m-bit words, a range of values from 0 to 2**n1 and from 2**m2**n to 2**m1 being excluded values on said SDI channel. The method comprises the steps of grouping the words to be transmitted, detecting if at least one of the words of the group contains a number of MSB's equal to one, and then recoding these MSBs and adding a constant, in order that no excluded values are obtained. Supplementary bits signal groups that have been recoded.

The present disclosure relates to a signal processing device, a signal processing method, a program, and a signal transmission system, capable of enabling video switching in frame units of an original video signal. A pixel thinning control unit thin out every other pair of two neighboring samples of each line from N consecutive frames of a video signal including an m*n(48P-60P)*N/r:g:b/10-bit or 12-bit signal in which the number of pixels per frame exceeds the number of pixels specified in an HD format at intervals of 2N lines, map the thinned every other pair of two neighboring pixel samples to first to 4N-th sub images including an m*n/48P-60P/r:g:b/10-bit or 12-bit signal, and arrange a vertical blanking region between two of N regions in which pixel samples of respective frames of the first video signal are mapped in each sub image.

The present invention relates to an input/output system for an ultra high definition image, and more specifically, to an input/output system for an ultra high definition image that may receive an ultra high definition image signal from an external device, process the signal in real time, and output the processed ultra high definition image signal. For this purpose, a system configured to convert data having various resolutions into UHD data of the present invention includes a content input/output device configured to provide data received from a data providing device to an editing device and provide the data received from the editing device to a content reproducing device, and an editing device configured to convert the data received from the content input/output device into UHD data and provide the result to the content input/output device.