A pixel array includes pixel circuits including a first pixel circuit having first and second split floating diffusions receiving charge from first and third photodiodes through first and third transfer transistors, and from second and fourth photodiodes through second and fourth transfer transistors, respectively. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits. A dual floating diffusion transistor is coupled between the first and second split floating diffusions and the third and fourth split floating diffusions to bin charges in the first, second, third, and fourth floating diffusions.

A pixel array includes pixel circuits including a first pixel circuit having first and second split floating diffusions receiving charge from first and third photodiodes through first and third transfer transistors, and from second and fourth photodiodes through second and fourth transfer transistors, respectively. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits. A dual floating diffusion transistor is coupled between the first and second split floating diffusions and the third and fourth split floating diffusions to bin charges in the first, second, third, and fourth floating diffusions.

According to embodiments of the present disclosure, an image processing apparatus for processing image data captured by an image sensor configured to set exposure area by area includes a calculation unit configured to calculate an exposure value of each of the areas, and a correction unit configured to, in a case where the exposure value of each of the areas does not fall within a range based on a reference exposure value, correct the exposure value of each of the areas so that the exposure value approaches an upper limit or lower limit of the range.

According to embodiments of the present disclosure, an image processing apparatus for processing image data captured by an image sensor configured to set exposure area by area includes a calculation unit configured to calculate an exposure value of each of the areas, and a correction unit configured to, in a case where the exposure value of each of the areas does not fall within a range based on a reference exposure value, correct the exposure value of each of the areas so that the exposure value approaches an upper limit or lower limit of the range.

When imaging bright objects, a conventional detector array can saturate, making it difficult to produce an image with a dynamic range that equals the scene's dynamic range. Conversely, a digital focal plane array (DFPA) with one or more m-bit counters can produce an image whose dynamic range is greater than the native dynamic range. In one example, the DFPA acquires a first image over a relatively brief integration period at a relatively low gain setting. The DFPA then acquires a second image over longer integration period and/or a higher gain setting. During this second integration period, counters may roll over, possibly several times, to capture a residue modulus 2.sup.m of the number of counts (as opposed to the actual number of counts). A processor in or coupled to the DFPA generates a high-dynamic range image based on the first image and the residues modulus 2.sup.m.

A solid-state imaging device includes pixels including a photoelectric converter, a holding portion, and a transfer unit transferring charges from the photoelectric converter to the holding portion, and outputting a signal based on charges held in the holding portion, a signal line the signal is output from the pixels, a clipping unit limiting signal level so that it falls within a range having an upper limit or a lower limit determined by a clipping level, a transfer control unit controlling the transfer unit so that the charges generated during one exposure period are transferred through transfer operation performed at frequency variable but at least once, and a clipping level control unit controlling so that the clipping level is set to first clipping level when the transfer operation is performed at first frequency, and is set to second clipping level when the transfer operation is performed at second frequency.

An image sensor includes a unit pixel that includes a photoelectric converter configured to accumulate electric charges generated based on incident light, and an electric charger configured to store the electric charges transferred from the photoelectric converter, and a corrector configured to correct a signal corresponding to the electric charges output from the electric charger based on a transfer condition when the electric charges are transferred from the photoelectric converter to the electric charger.

An image device transfers charges of a previous frame from the holding units to the amplification units, during a read-out period of each frame, the read-out period includes a period in which a plurality of overflow transistors are in an on-state and a first period in which a plurality of photoelectric conversion units accumulate charges, and, during a second period following the first period, the plurality of photoelectric conversion units of the plurality of pixels accumulate charges while the plurality of holding units of the plurality of pixels hold the charges accumulated during the first period. During the first and second periods, each of the plurality of pixels performs a plurality of times of charge transfers from the photoelectric conversion unit to the holding unit. The plurality of times of charge transfers including a charge transfer performed at the end of the second period.

An imaging apparatus changes a multiplication factor of an avalanche photodiode (APD) at one of (i) a first timing subsequent to an exposure period of a first frame in a first vertical scanning period and a readout period of the first frame in a second vertical scanning period, and previous to an exposure period of a second frame in a third vertical scanning period, and (ii) a second timing subsequent to an exposure period of the first frame in the first vertical scanning period, and previous to a readout period of the first frame and an exposure period of the second frame which are provided in parallel in the second vertical scanning period.

An imaging device including a pixel array section functioning as a light receiving section which includes photoelectric conversion devices and in which a plurality of pixels, which output electric signals when photons are incident, are disposed in an array; a sensing circuit section in which a plurality of sensing circuits, which receive the electric signals from the pixels and perform binary determination regarding whether or not there is an incidence of photons on the pixels in a predetermined period, are arrayed; and a determination result integration circuit section having a function of integrating a plurality of determination results of the sensing circuits for the respective pixels or for each pixel group, wherein the determination result integration circuit section derives the amount of photon incidence on the light receiving section by performing photon counting for integrating the plurality of determination results in the plurality of pixels.