In a solid-state imaging device, a first substrate has a plurality of pixels and a plurality of first control signal lines. The plurality of first control signal lines are connected to pixels of each row. The second substrate includes a plurality of second control signal lines and a control circuit. The arrangement of each of the plurality of second control signal lines on the second substrate corresponds to the arrangement of a corresponding one of the plurality of first control signal lines on the first substrate. The connection portion has a plurality of control connections and a plurality of readout connections. Each of the plurality of control connections is connected to one of the plurality of first control signal lines and a corresponding one of the plurality of second control signal lines.

An image sensor includes a pixel array including a first pixel and a second pixel which are connected to a first column line, and a row driver configured to control a read operation of the second pixel. A voltage of the first column line is determined based on a higher voltage among a voltage of a floating diffusion node of the first pixel and a voltage of a floating diffusion node of the second pixel during the read operation of the second pixel.

Provided are a pixel array and an image sensor including the same. The pixel array includes a plurality of sub-pixels adjacent to each other and a readout circuit connected to the plurality of sub-pixels through a floating diffusion node. Each of the sub-pixels includes a photoelectric conversion element, an overflow transistor connected to the photoelectric conversion element, a phototransistor connected to the photoelectric conversion element and the overflow transistor, and a storage element connected to the phototransistor.

Provided are a pixel array and an image sensor including the same. The pixel array includes a plurality of sub-pixels adjacent to each other and a readout circuit connected to the plurality of sub-pixels through a floating diffusion node. Each of the sub-pixels includes a photoelectric conversion element, an overflow transistor connected to the photoelectric conversion element, a phototransistor connected to the photoelectric conversion element and the overflow transistor, and a storage element connected to the phototransistor.

An imaging device according to an embodiment includes: a plurality of pixels (110) each including a photoelectric conversion element (20) and arranged in an array of matrix; a control line group (16) including a plurality of control lines for controlling each of pixels aligned in a row direction, each arranged in each of rows of the array; and a plurality of reading lines (VSL) arranged in each of columns for transferring a pixel signal read from each of pixels aligned in a column direction of the array, wherein the plurality of pixels includes: a first pixel (110GS) controlled by a control signal supplied from a first control line group including control lines in a first number among a plurality of control lines included in the control line group in each of pixels aligned in the row direction in at least one of rows of the array; and a second pixel (110RS) controlled by a control signal supplied from a second control line group including a control line in a second number smaller than the first number among a plurality of control lines included in the control line group.

An imaging device according to an embodiment includes: a plurality of pixels (110) each including a photoelectric conversion element (20) and arranged in an array of matrix; a control line group (16) including a plurality of control lines for controlling each of pixels aligned in a row direction, each arranged in each of rows of the array; and a plurality of reading lines (VSL) arranged in each of columns for transferring a pixel signal read from each of pixels aligned in a column direction of the array, wherein the plurality of pixels includes: a first pixel (110GS) controlled by a control signal supplied from a first control line group including control lines in a first number among a plurality of control lines included in the control line group in each of pixels aligned in the row direction in at least one of rows of the array; and a second pixel (110RS) controlled by a control signal supplied from a second control line group including a control line in a second number smaller than the first number among a plurality of control lines included in the control line group.

An imaging pixel formed by a photodetector connected to a reading circuit comprising: an integration capacitance, a transistor for resetting the integration capacitance, a coupling transistor between the photodetector and the integration capacitance, a memorisation capacitance, a second transistor for resetting the memorisation capacitance, a memorisation switch between the integration capacitance and the memorisation capacitance, to enable different configurations corresponding to different phases of assessing parameters of the pixel and in particular a ratio R=Cint/Cmem.

An imaging pixel formed by a photodetector connected to a reading circuit comprising: an integration capacitance, a transistor for resetting the integration capacitance, a coupling transistor between the photodetector and the integration capacitance, a memorisation capacitance, a second transistor for resetting the memorisation capacitance, a memorisation switch between the integration capacitance and the memorisation capacitance, to enable different configurations corresponding to different phases of assessing parameters of the pixel and in particular a ratio R=Cint/Cmem.

According to the present disclosure, an imaging element may include: a substrate or a well; a pinned photodiode disposed on the substrate; a floating diffusion region disposed on the substrate or the well; a first transfer gate transistor disposed between the pinned photodiode and the floating diffusion region a photodiode signal charge generated by the pinned photodiode to the floating diffusion region; one or more gate-controlled storages disposed on the substrate and storing a signal charge generated by the pinned photodiode as a storage signal charge; a storage-controlling gate electrode disposed adjacent to the gate-controlled storage; an overflow path disposed between the pinned photodiode and the gate-controlled storage and transferring the storage signal charge from the pinned photodiode to the gate-controlled storage; and a detecting node connected to the floating diffusion region, wherein the photodiode signal charge and the storage signal charge can be read at the detecting node.

Embodiments of pixel circuit, image sensor, image pickup device and methods for using the same are provided. In an example, the pixel circuit comprises a source module configured to output non-simultaneously a reference signal indicative of a reset level and an electrical signal indicative of incident light, a sampling module comprising a first sampling unit, a second sampling unit and a sampling switch, a first switch module configured to be electrically coupled between the source module and the sampling module, and a second switch module configured to be electrically coupled between the sampling module and a bus.