An imaging device includes a voltage generation circuit and an output circuit. The voltage generation circuit includes a first capacitance element including a fifth terminal. The voltage generation circuit is configured to provide the fifth terminal with a first voltage in accordance with a power source voltage so as to store an electric charge in the first capacitance element. The voltage generation circuit is configured to increase a voltage of the fifth terminal by a second voltage in accordance with the power source voltage so as to generate a control voltage having a greater absolute value than an absolute value of the power source voltage. The output circuit is configured to output the control voltage to at least one of a gate terminal of a reset transistor of a pixel and a gate terminal of a transfer transistor of the pixel.

Provided is a multilayer imaging device capable of both securing a wide sensitive region and securing an accumulated amount of charges. An imaging device according to an embodiment comprises a pixel, the pixel including a photoelectric conversion layer (15); a first electrode (11) positioned close to a first surface of the photoelectric conversion layer and electrically connected to the photoelectric conversion layer; a second electrode (16) positioned on a second surface opposite to the first surface of the photoelectric conversion layer; a charge accumulation electrode (12) disposed close to the first surface of the photoelectric conversion layer and spaced apart from the first electrode in a direction parallel to the first surface; and a third electrode (200) disposed at a position to have a portion overlapping a gap between the first electrode and the charge accumulation electrode in a direction perpendicular to the first surface.

Solid-state imaging elements are disclosed. In one example, an upstream circuit block generates a predetermined reset level and a plurality of signal levels each corresponding to an exposure amount, and causes capacitive elements, different from each other, to hold them. A selection circuit sequentially performs control to connect the capacitive element in which the reset level is held to a predetermined downstream node, control to disconnect capacitive elements from the downstream node, and control to connect the capacitive element in which any of the plurality of signal levels is held to the downstream node. A downstream reset transistor initializes a level of the downstream node when the capacitive elements are disconnected from the downstream node. A downstream circuit sequentially reads the reset level and the plurality of signal levels via the downstream node

A Complementary Metal Oxide Semiconductor (CMOS) Image Sensor (CIS), includes a pixel circuit, a VSL circuit, and an amplifier. The pixel circuit may generate a reset voltage and a signal voltage, based on a power supply connected to the pixel circuit and/or intensity of light captured by the pixel circuit. The VSL circuit may store pixel information in a pixel load based on settling a voltage at the pixel load to the signal voltage and/or set the voltage at the pixel load to a pixel reset voltage based on settling the voltage at the pixel load to the reset voltage. The amplifier may generate a voltage, based on varying a resistance at an input of the amplifier, to enable the VSL circuit to store the pixel information and/or set the voltage at the pixel load to the pixel reset voltage.

A Complementary Metal Oxide Semiconductor (CMOS) Image Sensor (CIS), includes a pixel circuit, a VSL circuit, and an amplifier. The pixel circuit may generate a reset voltage and a signal voltage, based on a power supply connected to the pixel circuit and/or intensity of light captured by the pixel circuit. The VSL circuit may store pixel information in a pixel load based on settling a voltage at the pixel load to the signal voltage and/or set the voltage at the pixel load to a pixel reset voltage based on settling the voltage at the pixel load to the reset voltage. The amplifier may generate a voltage, based on varying a resistance at an input of the amplifier, to enable the VSL circuit to store the pixel information and/or set the voltage at the pixel load to the pixel reset voltage.

A pixel includes a transfer gate, and a sample structure having a first sample stage and a second sample stage. The transfer gate and the first and the second sample stages are configured to be operated in conjunction with a light source in response to a control signal. The first sample stage is configured to sample a first sample value that depends on radiation incident on the photosensitive element from an object or a scene that is illuminated by the light source emitting light at a first output power, while the second sample stage is configured to sample a second sample value that depends on radiation incident on the photosensitive element from the object or the scene that is illuminated by the light source emitting light at a second output power. The first output power is different, in particular significantly different, from the second output power.

A pixel includes a transfer gate, and a sample structure having a first sample stage and a second sample stage. The transfer gate and the first and the second sample stages are configured to be operated in conjunction with a light source in response to a control signal. The first sample stage is configured to sample a first sample value that depends on radiation incident on the photosensitive element from an object or a scene that is illuminated by the light source emitting light at a first output power, while the second sample stage is configured to sample a second sample value that depends on radiation incident on the photosensitive element from the object or the scene that is illuminated by the light source emitting light at a second output power. The first output power is different, in particular significantly different, from the second output power.

An image pickup device having a pixel region in which pixels are arranged, and in which a multilayer wiring structure is disposed. Each pixel includes a photoelectric conversion unit, a charge accumulation unit, a floating diffusion, a light shielding portion covering the charge accumulation unit and opening above the photoelectric conversion unit, and a waveguide which overlaps at least partially a portion at which the light shielding portion opens in a plan view. The device includes an insulating film disposed below the optical waveguide. The insulating film has a refractive index higher than that of an interlayer insulating film. The insulating film is disposed closer to the photoelectric conversion unit than to the lowermost wiring layer among wiring layers of the multilayer wiring structure. The insulating film extends to a portion above the light shielding portion. The insulating film is wider than a lower portion of the optical waveguide.

Provided are a solid-state imaging device, a method for driving a solid-state imaging device and an electronic apparatus capable not only of having advanced global shutter and autofocus functions but also of sufficiently achieving single exposure high dynamic range (SEHDR) performance, thereby substantially realizing enhanced dynamic range and frame rate.

In an image capturing mode, a reading part controls driving of a conversion signal reading part such that the conversion signal reading part keeps first and second transfer transistors in a conduction state in the same transfer period and performs a read-out operation on a pixel signal corresponding to a sum of charges stored in a first photodiode and charges stored in a second photodiode with a first conversion gain and subsequently with a second conversion gain.

An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.