Patent classifications
H04N25/772
Photoelectric conversion apparatus and image capturing apparatus with A/D conversion and data transmission
A photoelectric conversion apparatus includes a pixel array having pixels arranged to form rows and columns and column signal lines configured to output noise signals and optical signals of the pixels, a driver configured to drive the pixels so that the optical signal is output following the noise signal from each pixel, A/D converters configured to perform A/D conversion to convert the noise signals output to the column signal lines into noise data and to subsequently perform A/D conversion to covert the optical signals output to the column signal lines into optical data, a data hold circuit, and a transmitter configured to transmit the noise data converted by the A/D converters to the data hold circuit and to subsequently transmit the optical data converted by the A/D converters to the data hold circuit.
Photoelectric conversion apparatus and image capturing apparatus with A/D conversion and data transmission
A photoelectric conversion apparatus includes a pixel array having pixels arranged to form rows and columns and column signal lines configured to output noise signals and optical signals of the pixels, a driver configured to drive the pixels so that the optical signal is output following the noise signal from each pixel, A/D converters configured to perform A/D conversion to convert the noise signals output to the column signal lines into noise data and to subsequently perform A/D conversion to covert the optical signals output to the column signal lines into optical data, a data hold circuit, and a transmitter configured to transmit the noise data converted by the A/D converters to the data hold circuit and to subsequently transmit the optical data converted by the A/D converters to the data hold circuit.
PIXEL ARRAY AREA OPTIMIZATION USING STACKING SCHEME FOR HYBRID IMAGE SENSOR WITH MINIMAL VERTICAL INTERCONNECTS
Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.
SOLID STATE IMAGING DEVICE, METHOD OF CONTROLLING SOLID STATE IMAGING DEVICE, AND PROGRAM FOR CONTROLLING SOLID STATE IMAGING DEVICE
A solid state imaging device includes: a pixel array unit that has a plurality of pixels 2-dimensionally arranged in a matrix and a plurality of signal lines arranged along a column direction; A/D conversion units that are provided corresponding to the respective signal lines and convert an analog signal output from a pixel through the signal line into a digital signal; and a switching unit that switches or converts the analog signal output through each signal line into a digital signal using any of an A/D conversion unit provided corresponding to the signal line through which the analog signal is transmitted, and an A/D conversion unit provided corresponding to a signal line other than the signal line through which the analog signal is transmitted.
SOLID STATE IMAGING DEVICE AND ELECTRONIC DEVICE
The present disclosure relates to a solid state imaging device and an electronic device from which a holding unit for holding information in a pixel can be eliminated. When a charge distribution unit distributes a pixel signal SIG to a first ADC, a pixel signal representing only reflection light is divided for allocation. When the charge distribution unit distributes a pixel signal SIG to a second ADC, a pixel signal representing background light and reflection light (partial) is divided for allocation. When the charge distribution unit distributes a pixel signal SIG to a third ADC, a pixel signal representing background light and reflection light (the rest) is divided for allocation. During a period in which no signal is acquired, a discharge transistor functions as an overflow portion for releasing electrical charge. The present disclosure can be applied to, for example, a solid state imaging device used for an imaging device.
RADIATION IMAGING APPARATUS AND RADIATION IMAGING SYSTEM
Provided is a radiation imaging apparatus, including: a plurality of pixels configured to output image signals corresponding to radiation; an image signal line configured to output the image signals; and a detection signal line configured to output a detection signal for detection of irradiation of the radiation, in which at least one of the plurality of pixels includes: a conversion element configured to convert the radiation into charge; a first switch configured to output the image signal corresponding to the charge via the image signal line; a storage capacitor including a first electrode and a second electrode, in which the first electrode is electrically connected to the conversion element to store the charge; and a second switch configured to electrically connect the second electrode and the detection signal line.
ACTIVE RESET CIRCUIT FOR RESET SPREAD REDUCTION IN SINGLE-SLOPE ADC
An image sensor comprises a pixel circuit including a reset transistor and configured to output a pixel signal; and a differential comparator including a pixel input, a reference input, and a comparator output, wherein one of a source or a drain of the reset transistor is connected to the comparator output. In this manner, an active reset method may be incorporated in the image sensor.
IMAGE SENSOR WITH CONTROLLABLE NON-LINEARITY
The present disclosure relates generally to apparatus and methods for image sensing, and, more particularly, to a multi-bit quanta image sensor (QIS) having a controllable (e.g., adjustably variable) exposure response characteristic. Some embodiments provide an apparatus and method wherein the non-linearity of the response of a multi-bit QIS is controllable (e.g., selectively variable) by dynamically choosing the bit depth n during AID conversion, and/or later (i.e., post-conversion) by firmware and/or software.
Image sensor including two boosting drivers
An image sensor comprises a row driver, a first row line which is connected to the row driver, first to fourth pixels connected to the first row line, first to fourth column lines connected to the first to fourth pixels and configured to receive respective first to fourth output signals from the first to fourth pixels, a boosting circuit connected to the first to fourth column lines, a second row line connected to the boosting circuit, first and second boosting drivers connected, respectively, to first and second terminals of the second row line. The boosting circuit may adjust voltage of the first and second output signals based on a first boosting enable signal received from the first boosting driver and may adjust a voltage of the third and fourth output signals based on a second boosting enable signal received from the second boosting driver.
Image sensor including two boosting drivers
An image sensor comprises a row driver, a first row line which is connected to the row driver, first to fourth pixels connected to the first row line, first to fourth column lines connected to the first to fourth pixels and configured to receive respective first to fourth output signals from the first to fourth pixels, a boosting circuit connected to the first to fourth column lines, a second row line connected to the boosting circuit, first and second boosting drivers connected, respectively, to first and second terminals of the second row line. The boosting circuit may adjust voltage of the first and second output signals based on a first boosting enable signal received from the first boosting driver and may adjust a voltage of the third and fourth output signals based on a second boosting enable signal received from the second boosting driver.