Described herein are architectures, platforms and methods for implementing scalable power in a wireless device. Multiple radio access technology architectures running different operating clock frequencies are supported by providing a scaled static clock frequency and dynamic clock frequencies by dynamically switching parallel paths of processing resources.

An electronic device includes a first graphic composer that composes first graphic data associated with a layer of a first composition type, a second graphic composer that composes second graphic data associated with a layer of a second composition type different from the first composition type. The electronic device also includes a processor that sets a composition type of each of a plurality of layers associated with at least one application to the first or second composition type, composes first graphic data corresponding to a layer set to the first composition type using the first graphic composer, compose the composed graphic data in the frame buffer and second graphic data corresponding to a layer set to the second composition type using the second graphic composer, and display the composed graphic data through a display connected with the electronic device.

A communication device is described comprising a receiver configured to receive data comprising information representing a required quality of service of the transmission of the data, hardware resources configured to perform a processing of the data and a controller configured to set a speed of the processing of the data by the hardware resources based on the determined required quality of service.

Methods and apparatuses pertaining to device-driven power scaling in advanced wireless modem architectures are described. A processor of a communication apparatus with time-varying peak processing capability during active operations negotiates with a wireless network, to which the communication apparatus is communicatively connected, to select one of a plurality of temporary capability states ranging between zero and peak performance of the communication apparatus. The processor initiates a capability state change such that the communication apparatus enters the selected temporary capability state from a current temporary capability state of the plurality of temporary capability states. The lifetime of the selected temporary capability state exceeds a control information period used by the wireless network to dynamically schedule data transmissions with the communication apparatus. The data transmissions between the communication apparatus and the wireless network are constrained according to the selected temporary capability state.

A power management approach for a mobile device includes comparing a battery provided power supply voltage to a reference voltage in order to generate an alarm signal. In response to the alarm signal the frequency of an operating clock applied to a system-on-chip is changed.

A motorized window treatment may provide a low-cost solution for controlling the amount of daylight entering a space through a window. The window treatment may include a covering material (e.g., a cellular shade fabric or a roller shade fabric), a drive assembly for raising and lowering the covering material, and a motor drive unit including a motor configured to drive the drive assembly to raise and lower the covering material. The motorized window treatment may comprise one or more battery packs configured to receive batteries for powering the motor drive unit. The batteries may be located out of view of a user of the motorized window treatment (e.g., in a headrail or in a battery compartment). The motorized window treatment may use various power-saving methods to lengthen the lifetime of the batteries, e.g., to reduce the motor speed to conserve additional battery power and extend the lifetime of the batteries.

A timing method and a clock device are provided. The method includes: determining a timing point according to a timing duration of a clock device, where a clock period of the clock device is T, the timing duration is N times of a first time duration, and the first time duration is equal to Q.sub.2T, where Q.sub.2=Q.sub.1 or Q.sub.2=Q.sub.1, and Q.sub.1=C/T, N is a positive integer, Q.sub.1 is not an integer, and C is a constant (210); and performing one adjustment on timing time of the clock device each time P first time durations elapse, where an amount of time for each adjustment is one clock period T, P=1/|Q.sub.2Q.sub.1| (220). Based on this method, accurate timing can still be effectively implemented when a ratio of a constant C (for example, 1.25 ms) to a clock period is not an integer.

A system includes a frequency-locked loop (FLL) circuit, a sensor-hub circuit and a processor. The FLL circuit is used to generate a low-frequency clock. The sensor-hub circuit is coupled to a number of sensors and is configured to periodically poll the sensors during polling periods and to detect sensor activities. The processor is coupled to the sensor-hub circuit and can process sensor signals from one or more active sensors. The processor is off during polling periods and is turned on when a sensor activity is detected. The polling periods are based on the low-frequency clock generated by the FLL circuit.

A first die is communicatively coupled to a first isolation communication channel and a second isolation communication channel and configured to send a first heartbeat signal over the first isolation communication channel. A second die is coupled to receive the first heartbeat signal from the first die over the first isolation communication channel and to supply a second heartbeat signal to the second isolation communication channel. The first die enters a first die low power mode responsive to detecting an absence of the second heartbeat signal and the second die enters a second die low power mode responsive to detecting an absence of the first heartbeat signal. The first and second die use low power oscillators in the low power mode to supply the heartbeat signals.

An electronic device and a method of controlling the electronic device are provided. A memory and a processor are electrically connected with the memory. The processor controls at least one of a change in a specified operation power, a change in a specified operation clock rate, and an operation state of a diversity module of the electronic device when the electronic device enters an inactive period after an active period associated with transmitting data has ended.