An electronic assembly is provided, including a wiring board, a control element, and a pair of first internal electrical connectors. The wiring board includes a mounting surface, a first patterned conductive layer, a plurality of second patterned conductive layers, a plurality of near conductive holes, a plurality of far conductive holes, and a first conductive path. The first patterned conductive layer is located between the mounting surface and the second patterned conductive layers. The control element is mounted on the mounting surface of the wiring board. The pair of first internal electrical connectors are mounted on the mounting surface of the wiring board, and are adapted for mounting a pair of memory modules. The first conductive path extends from the control element at least through the corresponding second patterned conductive layer and the first patterned conductive layer to the pair of first internal electrical connectors.

An integrated circuit package includes a substrate with traces for high speed communication that are subject to crosstalk. The traces include overlapping pads on different layers of the substrate, which can increase the mutual capacitance of the signal lines, which will offset the mutual inductance. Thus, the overlapping pads can reduce the crosstalk between the signal traces.

The present disclosure relates to a telecommunications jack including a housing having a port for receiving a plug. The jack also includes a plurality of contact springs adapted to make electrical contact with the plug when the plug is inserted into the port of the housing, and a plurality of wire termination contacts for terminating wires to the jack. The jack further includes a circuit board that electrically connects the contact springs to the wire termination contacts. The circuit board includes a multi-zone crosstalk compensation arrangement for reducing crosstalk at the jack.

An electronic device according to various embodiments of the disclosure may include a printed circuit board constructed with a layered structure of a plurality of boards, and may include, among the plurality of boards, a circuit board constructed around a first region to which an acoustic component is disposed, and having at least one slit constructed to block a low-frequency band noise.

A device may include a substrate having a first surface and a second surface, a first conductive terminal disposed over the first surface, a second conductive terminal spaced apart from the first conductive terminal in a first direction and disposed over the first surface, a first conductive auxiliary pattern disposed below the first conductive terminal and overlapping with the first conductive terminal, the first conductive auxiliary pattern being coupled to the second conductive terminal, and a second conductive auxiliary pattern disposed below the second conductive terminal and overlapping with the second conducive terminal, the second conductive auxiliary pattern being coupled to the first conductive terminal.

In a multilayer wiring board having through holes used in an electronic device, wiring is efficiently performed at high density while preventing crosstalk of differential signals. A wiring board includes: a plurality of pads arranged linearly at a predetermined pitch; a plurality of through holes arranged in parallel along an arrangement direction of the pads; and a wiring pattern connecting the pad to the through hole. Between the through holes connected to the pads which are connected to the ground via the wiring patterns, two through holes through which each of a pair of differential signals constituting a differential signal pair passes are provided such that a direction of a straight line connecting the two through holes is inclined to the arrangement direction of the pads.

Methods and systems for providing crosstalk compensation in a jack are disclosed. According to one method, the crosstalk compensation is adapted to compensate for undesired crosstalk generated at a capacitive coupling located at a plug inserted within the jack. The method includes positioning a first capacitive coupling a first time delay away from the capacitive coupling of the plug, the first capacitive coupling having a greater magnitude and an opposite polarity as compared to the capacitive coupling of the plug. The method also includes positioning a second capacitive coupling at a second time delay from the first capacitive coupling, the second time delay corresponding to an average time delay that optimizes near end crosstalk. The second capacitive coupling has generally the same overall magnitude but an opposite polarity as compared to the first capacitive coupling, and includes two capacitive elements spaced at different time delays from the first capacitive coupling.

An electronic device includes a first component carrier with a stack of at least one first electrically conductive layer structure and at least one first electrically insulating layer structure, and a second component carrier with a respective stack of at least one second electrically conductive layer structure and at least one second electrically insulating layer structure. The second component carrier is connected with the first component carrier so that a stacking direction of the first component carrier is angled with regard to a stacking direction of the second component carrier.

A pin map covers a surface area of a layer of a printed circuit board (PCB). The pin map includes a plurality of electrical designations for each pin in the pin map and a plurality of empty spaces within the pin map. Each electrical designation may be assigned to a pin on the pin map. Each electrical designation includes a positive polarity (P+) pin, a negative polarity (P−) pin, or an electrical ground (G) pin. If a space in the pin map does not have an electrical designation, then it may include an empty space/plain portion of the printed circuit board (PCB). The pin map may include a plurality of rows and a first repeating pin polarity pattern. The first repeating pin polarity pattern may include a lane unit tile. The pin map may help couple two circuit elements together that are attached to one layer of a PCB.

A printed circuit board includes a differential signal via pairs to route differential signal between layers of the printed circuit board. A first differential signal via pair is oriented in a first orientation and a second differential signal via pair is oriented perpendicular to the first orientation. The second differential signal via pair is located such that a midpoint of a first line segment drawn between centers of first and second vias of the second differential signal pair intersects a first ray drawn from a center of a first via of the first differential signal via pair through a center of a second via of the first differential signal via pair. Further, the second differential signal via pair is located such that the midpoint of the first line segment is at a characteristic via-to-via pitch distance for the printed circuit board from the center of the second via of the first differential signal via pair.