A manufacturing method of a circuit substrate includes the following steps. A core layer having a core dielectric layer, a first patterned circuit layer and a second patterned circuit layer is provided. An electroless plating nickel layer is formed on the first patterned circuit layer and the second patterned circuit layer. The electroless plating nickel layer has a first thickness, and the first thickness is between 1 micrometer and 10 micrometers. A reducing process is performed on the electroless plating nickel layer so that the electroless plating nickel layer is thinned from the first thickness to a second thickness to form a thinned electroless plating nickel layer. The second thickness is between 0.01 micrometers and 0.9 micrometers. An electroless plating palladium layer is formed on the thinned electroless plating nickel layer. A surface metal passivation layer is formed on the electroless plating palladium layer.

A printed circuit board includes a first signal line inside a first dielectric layer; a first ground conductor layer and a second ground conductor layer; a second signal line disposed on the first ground conductor layer; a signal via for connecting the first signal line and the second signal line; and ground vias formed surrounding the signal via. The ground vias include first ground vias formed at respective first points, second ground vias formed at respective second points. The first points are placed on the line of a first polygon, and the second points are placed on the line of a second polygon, and the distances between adjacent first points and those between adjacent second points are all equal to or shorter than a first distance, and at least one second point is placed within the first distance from each of the adjacent first points.

A printed wiring board includes a first insulating layer, a conductor layer on the first insulating layer, and a second insulating layer formed on the first insulating layer and covering the conductor layer. The conductor layer includes first, second and third circuits, the first circuit has first width of 15 μm or less, the first and second circuits have second space between the first and second circuits such that the second space has second width of 14 μm or less, the first and third circuits have third space between the first and third circuits such that the third space has third width of 20 μm or more, and the first circuit has first lower and upper surfaces, and second and third side walls such that second angle between the second wall and the first lower surface is larger than third angle between the third wall and the first lower surface.

A wiring board and a method for manufacturing the wiring board in which an initial Cu plated layer is formed by plating so as to cover the surface of a metallized layer and then the initial Cu plated layer is heated to be softened or melted. Copper in the softened or melted initial Cu plated layer enters into open pore portions of the metallized layer. In addition, during the heating, components of the metallized layer and components of the initial Cu plated layer are mutually thermally diffused. Consequently, when solidified later (that is, when the initial Cu plated layer becomes a lower Cu plated layer), the adhesiveness between the metallized layer and the lower Cu plated layer is improved due to, for example, an anchoring effect and a mutual thermal diffusion effect.

A component carrier with a double layer structure is illustrated and described. The double layer structure includes an electrically conductive patterned layer structure and a further patterned layer structure made of a two-dimensional material. The patterned layer structure and the further patterned layer structure have at least partly the same pattern. In an embodiment the component carrier includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure and at least one double layer structure connected with the stack.

A radio frequency connector includes a substrate, a first ground plane disposed upon the substrate, a signal conductor having a first contact point, with the first contact point being configured to electrically mate with a second contact point, and a first ground boundary configured to electrically mate with a second ground boundary, with the first ground boundary being formed as an electrically continuous conductor within the substrate.

Disclosed herein is an antenna device that includes: a substrate having a plurality of insulating layers laminated in a z-direction; a first ground pattern formed on a first insulating layer; a first radiating conductor pattern formed on a second insulating layer; a second ground pattern constituted by a first via conductor provided so as to penetrate at least two insulating layers; and a second radiating conductor pattern constituted by a second via conductor provided so as to penetrate at least one insulating layer. The first radiating conductor pattern overlaps the first ground pattern in the z-direction. The second radiating conductor pattern overlaps the second ground pattern in a y-direction.

A printed wiring board includes a first resin insulating layer, a second resin insulating layer formed on a surface of the first layer, and a conductor layer formed on the surface of the first layer such that the second layer is covering the conductor layer and that the conductor layer includes first, second, third, fourth, fifth, and sixth circuits such that the third and fourth circuits are sandwiching the first circuit and that the fifth and sixth circuits are sandwiching the second circuit. Widths between the first and third circuits and between the first and fourth circuits are 5 μm to 14 μm, and when a width between the second and fifth circuits and a width between the second and sixth circuits is 20 μm or more, the upper surface of the first circuit, and the upper surface and side walls of the second circuit are formed to have unevenness.

A circuit substrate comprising, in the following stacked order, a resin base material 1 having a dielectric loss tangent of 0.015 or lower, a polyaniline layer 2 comprising a substituted or unsubstituted polyaniline, and a metal layer 3, wherein the metal layer 3 has a surface roughness Rz.sub.JIS of 0.5 μm or less at the surface on the side of the polyaniline layer 2.

Provided is a conductive pattern having at least one unit conductive pattern forming one touch pixel according to an aspect of the present invention. The at least one unit conductive pattern includes a plurality of nanostructures each having opposite ends. A ratio of nanostructures, both opposite ends of which are in contact with edges of the at least one unit conductive pattern to all nanostructures included in the at least one unit conductive pattern is 70% or more.