A terahertz carrier sending apparatus and a terahertz carrier receiving apparatus include a feed transmission line configured to receive an electrical signal sent by a radio frequency sending circuit. A mode excitation structure is configured to excite a terahertz signal. A mode conversion structure includes an inner cavity whose inner wall is metal. A circuit board is configured to fasten the feed transmission line and the mode excitation structure. The mode conversion structure further includes a positioning slot. A part of the circuit board and the mode excitation structure are inserted into the inner cavity of the mode conversion structure. A plurality of metal through holes are distributed on both sides of the mode excitation structure. A boundary of the positioning slot is metal and press-fitted on the metal through holes on the both sides of the mode excitation structure.

A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the k.sup.th module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1).sup.th module clock signal terminal; and a fourth signal line for connecting the (k+1).sup.th module clock signal terminal to a 2k.sup.th module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.

A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the k.sup.th module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1).sup.th module clock signal terminal; and a fourth signal line for connecting the (k+1).sup.th module clock signal terminal to a 2k.sup.th module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.

A multilayer circuit board includes a plurality of electrically conductive rear pads for termination of a plurality of wires and a plurality of electrically conductive front pads for insertion into a connector. A plurality of pairs of substantially parallel traces extend between and connect the front pads to the rear pads. At least a first pair of traces and the front and rear pads connected thereto are disposed in a same layer of the multilayer circuit board. At least a second pair of traces is disposed in a same layer, and the rear and front pads connected thereto are disposed in a different layer of the multilayer circuit board. At least a third pair of traces are disposed in different layers of the multilayer circuit board. For each trace extending between and connecting the front and rear pads corresponding to the trace, the trace comprises no more than two vias.

A dielectric substrate has a first surface including a first terminal joint and a second terminal joint arranged along a first side surface. A first lead terminal is bonded to the first terminal joint with a bond. A second lead terminal is bonded to the second terminal joint with a bond. The first lead terminal includes a first base bonded to the first terminal joint and a first lead extending from the first base. The second lead terminal includes a second base bonded to the second terminal joint and a second lead extending from the second base. The first lead terminal includes the first base having a larger thickness than the first lead.

A wideband termination circuit layout is provided for high power applications. The circuit layout may include a dielectric layer having a first surface and a second surface. The circuit layout may also include an input port disposed over the first surface. The circuit layout may further include at least two resistive film patches disposed over the first surface of the dielectric layer and a tuning line between the at least two resistive films disposed over the first surface of the dielectric layer. The at least two resistive film patches are connected in series with the at least one tuning line.

Embodiments described herein relate to a method for modifying transmission line characteristics. The method may include: making a first determination of a null frequency of an input signal to a transmission line; performing an analysis to make a second determination of a wavelength of the input signal using, at least in part, the null frequency; making a third determination, based on the analysis, of a half wavelength of the input signal; calculating, based on the half wavelength, a total stub length; and adding a trace to a stub associated with a via, wherein the stub and the trace are a length that is at least a portion of the half wavelength of the input signal.

A coaxial power sensor assembly configured to provide a broadband matched termination utilizing coplanar waveguide topology while simultaneously providing a source of heat energy for a surface mount chip thermistor element to measure applied input power. The coaxial thermal power sensor is comprised of a thin film resistive device on a dielectric substrate and a surface mount chip thermistor element placed in close planar proximity to the resistive device in order to maximize the heat flux via a closely coupled thermal path to the thermistor and alter the bias current through the resistance to be measured. The power sensor is intended to function from DC to 70 GHz, but the same should not be construed as a limitation.

Example embodiments relate to power dividers. One example power divider includes a dielectric unit that includes one or more dielectric layers and has a first surface and a second surface. The power divider also includes a first transmission line unit being of a coplanar type or a stripline type. The first transmission line unit includes a plurality of first transmission lines, each first transmission line including a respective first line segment and a respective second line segment. The first transmission line unit also includes a first dielectric layer. The power divider also includes a second transmission line unit. The second transmission line unit includes a second transmission line. The second transmission line unit also includes a second dielectric layer. Further, the power divider includes a first via. In addition, the power divider includes a plurality of second vias distributed around the first via.

Embodiments described herein relate to a method for modifying transmission line characteristics. The method may include: making a first determination of a null frequency of an input signal to a transmission line; performing an analysis to make a second determination of a wavelength of the input signal using, at least in part, the null frequency; making a third determination, based on the analysis, of a half wavelength of the input signal; calculating, based on the half wavelength, a total stub length; and adding a trace to a stub associated with a via, wherein the stub and the trace are a length that is at least a portion of the half wavelength of the input signal.