An integrated circuit according to one or more embodiments may include a terminal to which an impedance element and a power supply having a predetermined potential can be connected. The integrated circuit may be configured to change a potential of one of electrodes of the impedance element connected to the terminal, detect a change in electrical characteristics of the terminal based on characteristics of the impedance element when the potential of the one electrode of the impedance element is changed, to determine a setting condition among a plurality of setting conditions that are used for an operation of the integrated circuit, store the setting condition in a storage, and use the setting condition stored in the storage for the operation of the integrated circuit.

A dielectric substrate has a first surface including a first terminal joint and a second terminal joint arranged along a first side surface. A first lead terminal is bonded to the first terminal joint with a bond. A second lead terminal is bonded to the second terminal joint with a bond. The first lead terminal includes a first base bonded to the first terminal joint and a first lead extending from the first base. The second lead terminal includes a second base bonded to the second terminal joint and a second lead extending from the second base. The first lead terminal includes the first base having a larger thickness than the first lead.

An electronic device is provided. The electronic device includes a board including a first conductive line, a second conductive line, a ground plane, and a conductive via hole connecting the first conductive line and the ground plane, at least one electronic component disposed in the board, an insulation member covering the at least one electronic component, and a conductive layer, the conductive layer includes a first part formed on a surface of the insulation member, a second part extending from an edge of the first part and electrically connected to the first conductive line, and a third part spaced apart from the second part and electrically connected to the second conductive line, and the electronic device includes at least one transmission line constituted by the second conductive line and the third part of the conductive layer.

A circuit can include a closed loop bus line having a plurality of connections. The circuit can include a plurality of integrated circuits disposed on the close loop bus line at a respective connection of the plurality of connections. One or more of the integrated circuits can be configured to drive a signal on the closed loop bus line. The closed loop bus line can be configured to prevent signal reflection. For example, in certain embodiments, there are no termination resistors at any of the terminations to reduce size, weight, and/or part count of the circuit.

Performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip and a chip component that are electrically connected to each other via a wiring substrate. The semiconductor chip includes an input/output circuit and an electrode pad electrically connected to the input/output circuit and transmitting the signal. The chip component includes a plurality of types of passive elements and includes an equalizer circuit for correcting signal waveforms of the signal, and electrodes electrically connected to the equalizer circuit. The path length from the signal electrode of the semiconductor chip to the electrode of the chip component is 1/16 or more and 3.5/16 or less with respect to the wavelength of the signal.

A high-frequency terminator includes a dielectric substrate, a metal layer provided on a back surface of the dielectric substrate, a transmission line provided on a front surface of the dielectric substrate, a resistor provided on the front surface of the dielectric substrate and connected to the transmission line, and a conductor electrically connecting the resistor and the metal layer. The dielectric substrate includes a first substrate part having a first thickness in a direction from the back surface toward the front surface, and a second substrate part having a second thickness in the direction that is less than the first thickness. The transmission line extends from the first substrate part to the second substrate part and is connected to the resistor on the second substrate part. The conductor electrically connects the metal layer and the resistor at the second substrate part.

An example system includes a communication channel and at least one tuning structure coupled to the communication channel. The tuning structure includes a branch of the communication channel. The tuning structure is to dissipate energy from the communication channel at least at one selected wavelength. The branch of the communication channel is a terminated portion.

A flexible printed circuit board includes: a board having a top surface and a back surface; a signal line on the top surface; a ground line on the back surface and overlapping with the signal line; a first signal terminal extending along a first direction in the top surface, the first signal terminal including a first via-hole and electrically connected with the signal line; a first ground terminal next to the first signal terminal along a second direction intersecting the first direction on the top surface, the first ground terminal including a second via-hole electrically connected with the ground line; and a second ground terminal next to the first signal terminal in a side opposite to the first ground terminal along the second direction on the top surface, the second ground terminal including a third via-hole electrically connected with the ground line.

Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.

Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.