In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.

A wiring board includes a first electrically-conductive layer; and a first resin layer covering the first electrically-conductive layer, the first resin layer including a resin portion and inorganic insulating particles dispersed in the resin portion. The first resin layer has a first layer region which is in contact with one main surface and side surfaces of the first electrically-conductive layer, and a second layer region which is located on a side of the first layer region which side is opposite to the first electrically-conductive layer. The inorganic insulating particles include a plurality of first inorganic insulating particles contained in the first layer region, and a plurality of second inorganic insulating particles contained in the second layer region. A content rate of the first inorganic insulating particles in the first layer region is lower than a content rate of the second inorganic insulating particles in the second layer region.

A land grid array (LGA) includes a grid array of metal pads plated directly onto a printed circuit board, and a discrete metal pad soldered to each of the plated metal pads in the grid array. Each discrete metal pad has an exposed contact surface after soldering, and a thickness of each discrete metal pad is selected as a function of location in the grid array so that the discrete pads provide a locus of exposed surfaces having greater flatness than the printed circuit board.

A printed wiring board includes first, second, and third wiring layers, first and second insulating members, and first and second vias. The first wiring layer includes a recognition mark and a first wiring on a first surface. The second wiring layer includes a first pad and a second wiring. The third wiring layer includes a third wiring. The first via penetrates the first insulating member and electrically connects the recognition mark to the first pad. The second via penetrates the second insulating member and electrically connects the first pad to the third wiring. The first pad and the first and second vias are in a region within an outer perimeter of the recognition mark when viewed from a direction orthogonal to the first surface.

A package substrate includes an inner interlayer, a first conductor layer, a second conductor layer, an outermost interlayer, an outermost conductor layer including first and second pads to mount electronic components, vias including first and second vias such that the first vias are connecting the first conductor layer and first pads and the second vias are connecting the first conductor layer and second pads, and skip vias penetrating through the outermost and inner interlayers such that the skip vias are connecting the outermost and second conductor layers. Sum of insulation distances (t1, t2) is in range of 40 μm or less to 10 μm or more, where the insulation distance (t1) is insulation distance between the outermost and first conductor layers and the insulation distance (t2) is insulation distance between the first and second conductor layers, and difference between the insulation distances (t1, t2) is less than 5 μm.

A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

A co-axial structure includes a substrate, a first conductive structure, a second conductive structure, and an insulating layer. The substrate includes a first surface. The first conductive structure includes a first circuit deposited on the first surface and a first via penetrating the substrate. The second conductive structure includes a second circuit deposited on the first surface and a second via penetrating the substrate. The first via and the second via extend along a first direction. The first circuit and the second circuit extend along a second direction, and the second direction is perpendicular to the first direction. The insulating layer is located between the first via and the second via. The insulating layer includes a filler. The first conductive structure and the second conductive structure are electrically insulated. The first circuit and the second circuit are coplanar.

A wiring board includes: a base material including, on one side of the base material, a protruding part that protrudes toward an outside, wherein the protruding part has a shape in which a center portion of a principal surface rises from the outer periphery, and a plurality of external connection terminals is arranged on the principal surface. A composite substrate includes: the above-mentioned wiring board and a metallic frame member, wherein the frame member includes an opening whose shape is corresponding to a shape in a plan view of the protruding part, and the frame member is arranged such that the opening surrounds the protruding part to fill a periphery of the protruding part. An electric device includes: an electric element on a right face of the wiring board.

The present application provides a method of bonding an integrated circuit chip to a display panel. The method includes forming a plurality of first bonding pads in a bonding region on a first side of the display panel; forming a plurality of vias extending through the display panel in the bonding region; subsequent to forming the plurality of vias, disposing an integrated circuit chip having a plurality of second bonding pads on a second side of the display panel substantially opposite to the first side, the plurality of second bonding pads being on a side of the integrated circuit chip proximal to the display panel; and electrically connecting the plurality of first bonding pads respectively with the plurality of second bonding pads by forming a plurality of connectors respectively in the plurality of vias.

Provided is an FPC, including a first row of gold fingers and a second row of gold fingers disposed on a same layer, and multiple first connection lines. The first row of gold fingers includes multiple first gold fingers extending in a first direction and arranged in a second direction. The second row of gold fingers includes multiple second gold fingers extending in the first direction and arranged in the second direction. The multiple first connection lines are disposed in a different layer from the second row of gold fingers, electrically connected to the multiple first gold fingers, and insulated from the multiple second gold fingers and extend to an area where the second row of gold fingers is located. The first connection line includes a first wire and a second wire. The first wire includes a first portion, a second portion and a third portion connected in sequence.