A component carrier with a stack including at least one electrically insulating layer structure and at least one electrically insulating structure has a tapering blind hole formed in the stack and an electrically conductive plating layer extending along at least part of a horizontal surface of the stack outside of the blind hole and along at least part of a surface of the blind hole. A minimum thickness of the plating layer at a bottom of the blind hole is at least 8 μm.

A Printed Circuit Board (PCB) includes a via extending through at least one layer of the PCB. The PCB may also include a first catch pad connected to the via and located within a first metal layer of the PCB. The first catch pad may have a first size. The PCB may further include a second catch pad connected to the via and located within a second metal layer of the PCB. The second catch pad may have a second size greater than the first size. The second catch pad may overlap horizontally with a portion of a metallic feature in the first metal layer to obstruct light incident on a first side of the PCB from transmission to a second side of the PCB through a region of dielectric material near the via.

A wiring substrate includes a first insulating layer, a first conductor layer, a second insulating layer, a second conductor layer, a connection conductor penetrating through the second insulating layer and connecting the first and second conductor layers, and a coating film formed on a surface of the first conductor layer such that the coating film is adhering the first conductor layer and the second insulating layer. The first conductor layer includes a conductor pad and a wiring pattern such that the conductor pad is in contact with the connection conductor and the wiring pattern is covered by the coating film, the conductor pad of the first conductor layer has a surface facing the second insulating layer and having a first surface roughness higher than a surface roughness of a surface of the wiring pattern, and the coating film has opening such that the opening is exposing the conductor pad entirely.

In one aspect, a PCB is provided. The PCB includes at least one insulating layer, a blind slot, and at least one via. The at least on insulating layer includes a first surface and a second surface opposite the first surface. The blind slot is plated and formed in the at least one insulating layer, where the blind slot partially extends from the first surface to the second surface, and where the blind slot includes a conductive plating bonded along a major surface of the blind slot. The at least one via is electrically conductive and filled, where the at least one via is coupled with and extends between the conductive plating of the blind slot and the second surface of the at least one insulating layer.

A printed circuit board includes an insulating layer; a recess portion disposed on one surface of the insulating layer; and a circuit layer disposed on the one surface of the insulating layer and including a signal pattern and a ground pattern. At least a portion of the ground pattern covers at least a portion of the recess portion.

Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.

A wiring board according to the present disclosure includes a first insulation layer including a first surface, a land located on the first insulation layer and including a second surface, a second insulation layer located at the first surface of the first insulation layer and including a via hole extending over the second surface of the land, and a via-hole electrical conductor located in the via hole. The land includes a plurality of recessed portions on the second surface, and at least one recessed portion selected from the plurality of recessed portions includes a buffer body containing resin. The via-hole electrical conductor is in contact with the second surface of the land and the buffer body.

A printed circuit board (PCB) for three-dimensional (3D) packaging that may facilitate packaging multiple electronic components therein is provided. The PCB may include one or more loading pads formed around signal or ground vias to facilitate impedance control and reduce likelihood of signal distortion. The loading pads may be formed on a plane in a body of a dielectric layer configured to form the PCB.

A wiring substrate includes a wiring layer that includes a first pad on which a first recess portion is formed and a second pad on which a second recess portion is formed; an insulating layer that includes a first opening portion penetrating to the first recess portion and a second opening portion penetrating to the second recess portion; a first metal layer filling each of the first opening portion and the second opening portion, extending on an upper surface of the insulating layer, and including a third recess portion and a fourth recess portion; and a second metal layer a part of which is stored in the third recess portion and the fourth recess portion, wherein the first metal layer has a uniform thickness at a portion extending on the upper surface, and the fourth recess portion is deeper than the third recess portion.